Solid state electromagnetic radiation detector FET array
AssigneeMinnesota Mining and Manufacturing Company
InventorsNang T. Tran, Neil W. Loeding, David V. Nins
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Abstract
The present invention provides a large area, high pixel density solid state radiation detector with a real-time and a non-destructive read-out. The solid state detector comprises a plurality of field effect transistors deposited onto a substrate to form an array. A planarization layer is deposited over the array of transistors. An energy sensitive layer is deposited onto the planarization layer. Means is provided for electrically connecting the energy sensitive layer with each transistor of the array. A top electrode layer is deposited onto the energy sensitive layer. The solid state detector also comprises circuitry means for providing electronic read-out from each FET of the array.
Claims31
A solid state detector for detecting electromagnetic radiation, comprising:
- (a) a substrate;
- (b) a plurality of field effect transistors deposited onto the substrate to form an array wherein each field effect transistor has a gate electrode;
- (c) a planarization layer deposited over the array of field effect transistors;
- (d) an energy sensitive layer deposited onto the planarization layer;
- (e) a plurality of bottom electrodes interposed between the planarization layer and the energy sensitive layer, wherein each bottom electrode is electrically coupled to the gate electrode of a single FET;
- (f) a top electrode layer deposited onto the energy sensitive layer;
- and
- (g) circuitry means for providing electronic read-out from each field effect transistor of the array.
A solid state detector for detecting electromagnetic radiation, comprising:
- (a) a substrate;
- (b) a plurality of thin film, field effect transistors deposited onto the substrate and arranged in rows and columns to form an array, wherein each transistor has a source electrode, a drain electrode, a gate electrode, and a gate dielectric layer having a gate capacitance;
- (c) a plurality of source lines for linking the source electrodes in each row of transistors;
- (d) a plurality of drain lines for linking the drain electrodes in each column of transistors;
- (e) a planarization layer deposited over the array for electrically isolating the source lines from the drain lines;
- (f) an energy sensitive layer deposited over the planarization layer, wherein the energy sensitive layer has an additional capacitance;
- (g) a plurality of bottom electrodes interposed between the planarization layer and the energy sensitive layer, wherein each bottom electrode is electrically coupled to the gate electrode of a single FET;
- and
- (h) a top electrode layer deposited onto the energy sensitive layer.
Dependencies are inferred from the claim text.