US 5,182,521 AGranted

Time-multiplexed switched capacitor circuit having reduced capacitance

AssigneeThe University of Melbourne

InventorsJoseph S. Chang, Yit C. Tong

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Abstract

A time-multiplexed switched capacitor circuit in which certain capacitors are shared during local time periods of a global time period to allow the total capacitance of the circuit to be reduced. Corresponding savings in chip area in an integrated circuit implementation and component savings in a discrete implementation may be achieved. The invention is particularly applicable to a multiplexed circuit comprising an array of capacitors including first and second common capacitors and first and second pluralities of capacitors. The capacitors may be switched into and out of the multiplexed circuit during different local time periods. The first common capacitor may be switched into the circuit when any one of the first plurality of capacitors is involved in the operation of the multiplexed circuit thus reducing the size of that one capacitor of the first plurality of capacitors. In a similar fashion, the first and second common capacitors may be switched into the circuit when any one of the second plurality of capacitors is involved in the operation of the multiplexed circuit.

An n-channel Switched Capacitor filter realized as a time multiplexed circuit and operative during n respective time periods to service respective channels of the filter, where n is an integer greater than 1, said filter having an input and an output and comprising:

first and second operational amplifiers, each operational amplifier having an inverting input, a non-inverting input and an output, said filter input being sampled during each of said time periods by the inverting input of said second operational amplifier and said filter output being provided at the output of the second operational amplifier, said output of said second operational amplifier being operatively applied to said inverting input of said first operational amplifier;
a first common capacitor;
a second common capacitor;
an array of n capacitors, respective capacitors of said array corresponding to respective channels of said filter, said array including a first plurality of n.sub.0 capacitors corresponding to n.sub.0 channels and a second plurality of n.sub.1 capacitors corresponding to n.sub.1 channels, where n.sub.0 +n.sub.1 =n;
first means operable during respective time periods corresponding to the n.sub.0 channels for connecting respective capacitors of said first plurality between the output of said first operational amplifier and the inverting input of said second operational amplifier;
second means operable during respective time periods corresponding to the n.sub.0 channels for connecting said first common capacitor between the output of said first operational amplifier and the inverting input of said second operational amplifier, so that during said respective time periods corresponding to the n.sub.0 channels, said first common capacitor is connected in parallel with said respective capacitors of said first plurality;
third means operable during respective time periods corresponding to the n.sub.1 channels for connecting respective capacitors of said second plurality between the output of said first operational amplifier and the inverting input of said second operational amplifier;
and
fourth means operable during respective time periods corresponding to the n.sub.1 channels for connecting said first and said second common capacitors between the output of said first operational amplifier and the inverting input of said second operational amplifier, so that during said respective time periods corresponding to the n.sub.1 channels, said first and said second common capacitors are connected in parallel with said respective capacitors of said second plurality, thereby reducing the total capacitance required in said filter.

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Abstract

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