Gate circuit having increased voltage handling capability
AssigneeU.S. Philips Corporation
InventorsFrank P. Behagel, Tiemen Poorter, Petrus A. C. M. Nuijten
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AssigneeU.S. Philips Corporation
InventorsFrank P. Behagel, Tiemen Poorter, Petrus A. C. M. Nuijten
Estimating the term…
A gate circuit includes an N-channel and a P-channel insulated gate field-effect transistor whose parallel-connected drain-source paths constitute an analog signal gate and a control circuit, connected to the respective gate electrodes, to turn on and/or turn off the two field-effect transistors. In order to handle signals whose voltage value is higher than the maximum permissible drain-source voltage in the on-state of the N-channel field-effect transistor, means are provided, for turning on the N-channel field-effect transistor at least at a drain-source voltage below a predetermined value. In an embodiment of the invention the means include delay means coupled to the control circuit for turning on the N-channel field-effect transistor with a delay relative to the P-channel field-effect transistor. In another embodiment of the invention the means include switching means arranged in series with the analog signal gate, for temporarily connecting the signal gate to at least one auxiliary voltage.
A gate circuit comprising an N-channel and a P-channel insulated-gate field-effect transistor, whose parallel-connected drain-source paths constitute a signal gate, and a control circuit connected to their respective gate electrodes to switch the state of the field-effect transistors, characterized in that means are provided for protecting said N-channel transistor from drain-source voltage overload, said protecting means comprising means for turning on the N-channel field-effect transistor at least a drain-source voltage lower than a selected value, in that said protecting means comprises delay means coupled to the control circuit for turning on the N-channel field-effect transistor with a delay relative to turning on the P-channel field-effect transistor, and in that the control circuit comprises an inverter circuit and a first and a second series arrangements of an N-channel and a P-channel field-effect transistor, which series arrangements are each coupled across a first and a second power-supply terminal, two field-effect transistors of a selected one conductivity type in said series arrangements being cross-coupled to each other to form a bistable trigger circuit, the gate electrode of a field-effect transistor of a selected other conductivity type in the first series arrangement being coupled by said inverter circuit;
Dependencies are inferred from the claim text.