Emitter emitter logic (EEL) and emitter collector dotted logic (ECDL) families

A logic circuit, comprising:

• (a) a plurality of logic gates, each of said plurality of logic gates comprising:
• (i) a plurality of first transistors, each of said plurality of transistors having a drain coupled to a first voltage terminal, a source coupled to a node, and a gate coupled to one each of a plurality of first input terminals;
• (ii) a second transistor having a source coupled to said node, a drain coupled to a second voltage terminal, and a gate coupled to said second voltage terminal;
• (iii) a diode having a cathode coupled to said node and an anode coupled to a first output terminal;
• and
• (b) a driver, coupled to said first output terminal, comprising means for amplifying a voltage and restoring logic levels at said output terminal.

A logic circuit, comprising:

• (a) a plurality of logic gates, each of said plurality of logic gates comprising:
• (i) a plurality of first transistors, each of said plurality of transistors having a collector coupled to a node, a base coupled to said node, and an emitter coupled one each to a plurality of first input terminals;
• (ii) a second transistor having a collector coupled to a first voltage terminal, a base coupled to said node, and an emitter coupled to a first output terminal;
• (iii) first resistive means coupled between said first output terminal and a second voltage terminal;
• (iv) second resistive means coupled between said node and said first voltage terminal;
• and
• (b) a driver, coupled to said first output terminal, comprising:
• means for amplifying a voltage and restoring logic levels at said first output terminal.

A logic circuit, comprising:

• (a) a plurality of logic gates, each of said plurality of logic gates comprising:
• (i) a first plurality of transistors, each of said first plurality of transistors having a drain coupled to a first node, a source coupled to a second node, and a gate coupled to one each of a plurality of input terminals;
• (ii) a first current source coupled between said first node and a first voltage terminal;
• (iii) a second current source coupled between said second node and a second voltage terminal;
• (iv) a first network coupled to said second node comprising:
• means for inverting the signal at said second node;
• (v) a second network coupled to said first network and a first output terminal comprising:
• means for discharging and charging a capacitive load coupled to said first output terminal;
• (b) a first logic gate, comprising:
• (i) a second plurality of transistors, each of said second plurality of transistors having a drain coupled a third node, a source coupled to a fourth node, and a gate coupled to one each of said first output terminals from said plurality of logic gates;
• (ii) a third current source coupled between said first voltage terminal and said third node;
• (iii) a fourth current source coupled between said second voltage terminal and said fourth node;
• and
• (iv) a third network coupled to said fourth node and a second output terminal comprising:
• means for charging and discharging capacitive loads coupled to said second output terminal.

A driver circuit, comprising:

• an input terminal;
• an output terminal;
• means for charging a capacitive load coupled to said output terminal;
• a network coupled to said output terminal, said network having a first state, comprising:
• means for rapidly discharging a capacitive load;
• and a second state, comprising:
• means for dissipating a minimum of power;
• means for generating an error voltage between a reference node and said output terminal in response to voltage changes at said input terminal;
• and
• means for switching said network between said first state and said second state in response to said error voltage.

A driver circuit, comprising:

• an input terminal;
• a first output terminal;
• a second output terminal;
• first means for charging a capacitive load coupled to said first output terminal;
• second means for charging a capacitive load coupled to said second output terminal;
• a first network coupled to said first output terminal and a second network coupled to said second output terminal, said first network and said second network each having a first state, comprising:
• means for rapidly discharging a capacitive load;
• and a second state, comprising:
• means for dissipating a minimum of power;
• and
• means for switching said first network and said second network between said first state and said second state in response to voltage changes at said input terminal.

A driver circuit, comprising:

• an input terminal;
• a pair of output terminals;
• a first stage, comprising:
• means for generating a pair of complementary signals in response to a comparison between a voltage at said input terminal and a reference voltage;
• means responsive to said pair of complementary signals for generating power in a second stage in order to charge and discharge capacitive loads coupled to said pair of output terminals;
• and
• means for setting said power in said second stage to any one of a plurality of discrete values within a range of values during fabrication of said driver.

A driver circuit, comprising:

• an input terminal;
• a pair of output terminals;
• a first stage, comprising:
• means for generating a first pair of voltages and a second pair of voltages in response to a voltage at said input terminal, and means responsive to a voltage at said input terminal for establishing a lower limit for said first pair of voltages and said second pair of voltages;
• and
• a second stage, comprising:
• means for discharging and charging capacitive loads coupled to said pair of output terminals in response to said first pair of voltages and said second pair of voltages.