Hysteresis comparator

A hysteresis comparator, comprising:

• first and second input terminals for receiving first and second input signals;
• at least one output terminal;
• first and second power supply terminals;
• a first transistor having a collector coupled to said first power supply terminal, a base coupled to said first input terminal, and an emitter;
• a second transistor having a collector coupled to said first power supply terminal, a base coupled to said first input terminal, and an emitter;
• a third transistor having a collector coupled to said first power supply terminal, a base coupled to said second input terminal, and an emitter;
• a fourth transistor having a collector coupled to said first power supply terminal, a base coupled to said second input terminal, and an emitter;
• a first current source coupled between the emitter of said first transistor and said second power supply terminal;
• a second current source coupled between the emitter of said second transistor and said second power supply terminal;
• a third current source coupled between the emitter of said third transistor and said second power supply terminal;
• a fourth current source coupled between the emitter of said fourth transistor and said second power supply terminal;
• and
• sensing and control circuitry for sensing differences between emitter voltages of said first, second, third, and fourth transistors and controlling, by supplying the sensed differences to said first, second, third and fourth current sources, a current of at least one of said first, second, third, and fourth current sources in accordance with the sensed differences to produce an offset voltage between said first and second input terminals.

A hysteresis comparator, comprising:

• first and second input terminals for receiving first and second input signals;
• first and second output terminals;
• first and second power supply terminals;
• a first transistor having a collector coupled to said first power supply terminal, a base coupled to said first input terminal, and an emitter;
• a second transistor having a collector coupled to said first power supply terminal, a base coupled to said first input terminal, and an emitter;
• a third transistor having a collector coupled to said first power supply terminal, a base coupled to said second input terminal, and an emitter;
• a fourth transistor having a collector coupled to said first power supply terminal, a base coupled to said second input terminal, and an emitter;
• a first current source coupled between the emitter of said first transistor and said second power supply terminal, said first current source comprising a fifth transistor having a collector coupled to the emitter of said first transistor, a base, and an emitter coupled to said second power supply terminal through a first resistor;
• a second current source coupled between the emitter of said second transistor and said second power supply terminal, said second current source comprising a sixth transistor having a collector coupled to the emitter of said second transistor, a base, and an emitter coupled to said second power supply terminal through a second resistor;
• a third current source coupled between the emitter of said third transistor and said second power supply terminal, said third current source comprising a seventh transistor having a collector coupled to the emitter of said third transistor, a base, and an emitter coupled to said second power supply terminal through said first resistor;
• a fourth current source coupled between the emitter of said fourth transistor and said second power supply terminal, said fourth current source comprising an eighth transistor having a collector coupled to the emitter of said fourth transistor, a base, and an emitter coupled to said second power supply terminal through said second resistor;
• a fifth current source having a first terminal coupled to said first power supply terminal and a second terminal;
• a ninth transistor having a collector coupled to said first output terminal, a base, and an emitter coupled to the second terminal of said fifth current source;
• a tenth transistor having a collector coupled to said second output terminal, a base, and an emitter coupled to the second terminal of said fifth current source;
• and
• sensing and control circuitry coupled to the bases of said fifth, sixth, seventh, eighth, ninth, and tenth transistors for sensing differences between emitter voltages of said first, second, third, and fourth transistors and controlling a current of at least one of said first, second, third, and fourth current sources in accordance with the sensed differences to produce an offset voltage between said first and second input terminals.

A hysteresis comparator, comprising:

• first and second input terminals for receiving first and second input signals;
• first and second output terminals;
• first and second power supply terminals;
• a first transistor having a collector coupled to said first power supply terminal, a base coupled to said first input terminal, and an emitter;
• a second transistor having a collector coupled to said first power supply terminal, a base coupled to said second input terminal, and an emitter;
• a first current source coupled between the emitter of said first transistor and said second power supply terminal, said first current source comprising (1) a third transistor having a collector coupled to the emitter of said first transistor, a base, and an emitter coupled to said second power supply terminal through a first resistor and (2) a fourth transistor having a collector coupled to the emitter of said first transistor, a base, and an emitter coupled to said second power supply terminal through a second resistor;
• a second current source coupled between the emitter of said second transistor and said second power supply terminal, said second current source comprising (1) a fifth transistor having a collector coupled to the emitter of said second transistor, a base, and an emitter coupled to said second power supply terminal through said first resistor and (2) a sixth transistor having a collector coupled to the emitter of said second transistor, a base, and an emitter coupled to said second power supply terminal through said second resistor;
• a seventh transistor having a collector coupled to said first output terminal, a base, and an emitter coupled to said second power supply terminal through a third resistor;
• an eighth transistor having a collector coupled to said second output terminal, a base, and an emitter coupled to said second power supply terminal through said third resistor;
• and
• sensing and control circuitry coupled to the bases of said third, fourth, fifth, sixth, seventh, and eighth transistors for sensing differences between emitter voltages of said first and second transistors and controlling a current of at least one of said first and second current sources in accordance with the sensed differences to produce an offset voltage between said first and second input terminals.