US 5,182,467 A · High performance multiplexer for improving bit error rate

Abstract

An apparatus and method for improving the bit error rate of multiplexed signals in a multiplexer system includes independently controlling two types of timing errors. The first type of timing error is related to the timing of transitions between alternating portions of the multiplexed output signal. The second type of timing error is related to the amplitude of the crossing points of the multiplexed signal portions. Varying the duty cycle of the clock signal to the multiplexer controls the transition between the alternating portions of the multiplexed output signal, and adding a voltage offset between single-ended components of the multiplexed output signal controls the amplitude of the crossing points between the one/zero and zero/one transitions of the multiplexed outut signal. The two types of timing errors are controlled with two separate control voltage ports that are independently and continuously variable in order to achieve the optimum bit error rate.

Claims23

Dependent claims

A multiplexer system comprising:

means for generating a variable duty cycle clock signal;
a two-to-one multiplexer having first and second data inputs for respectively receiving first and second input signals, a clock input for receiving the variable duty cycle clock signal, and an output for providing a multiplexed output signal;
means coupled to the output of the multiplexer for adjusting the amplitude of crossing points of the multiplexed signal to form an offset multiplexed output signal;
and
an output stage having an input for receiving the offset multiplexed output signal and an output for providing an error-corrected multiplexed output signal.

2 more elements

Dependencies are inferred from the claim text.

High performance multiplexer for improving bit error rate

Life of this patent

High performance multiplexer for improving bit error rate

Life of this patent

Abstract

Claims23