Metal silicide texturizing technique
AssigneeMicron Technology, Inc.
InventorsNavjot Chhabra, Gurtej S. Sandhu
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Abstract
In the present invention, a stable and uniform texturized surface of a conductive structure is developed by annealing, oxidizing and etching a layer of metal silicide that has been deposited over a semiconductive material. Using this process during fabrication of memory cell in a DRAM will increase storage node capacitance by creating texturized capacitor cell plates that will retain their textured surfaces throughout implementation of conventional DRAM fabrication processes.
Claims29
A process for texturizing a conductive structure fabricated on a silicon wafer, comprising the following steps:
- a) depositing a layer of polycrystalline silicon, said polycrystalline silicon conforming to existing topography of said silicon wafer;
- b) depositing a metal silicide superjacent said polycrystalline silicon layer;
- c) annealing said metal silicide thereby forming silicide grain size being approximately 1/10 the size of the conductive structure and silicon rich grain boundaries in said metal silicide film;
- d) oxidizing said metal silicide film thereby consuming silicon atoms int eh grain boundaries of said metal silicide film;
- and
- e) etching said oxide from top of said metal silicide thereby creating said texturized surface of said conductive structure;
- wherein said oxidizing step and said etching step are performed separately in order to first isolate said silicon atoms in the grain boundaries by said oxidizing step and then consume said oxidized silicon int he grain boundaries by said etching step.
A process for texturizing a conductive storage node capacitor cell plate in a semiconductor integrated memory circuit fabricated on a silicon wafer, comprising the following steps:
- a) depositing a layer of polycrystalline silicon, said polycrystalline silicon conforming to existing topography of said silicon wafer;
- b) depositing a metal silicide superjacent said polycrystalline silicon layer;
- c) annealing said metal silicide thereby forming silicide grain size being approximately 1/10 the size of the conductive structure and silicon rich grain boundaries in said metal silicide film;
- d) oxidizing said metal silicide film thereby consuming silicon atoms in the grain boundaries of said metal silicide film;
- and
- e) etching said oxide from top of said metal silicide thereby creating said texturized surface of said conductive structure;
- wherein said oxidizing step and said etching step are performed separately in order to first isolate said silicon atoms in the grain boundaries by said oxidizing step and then consume said oxidized silicon int he grain boundaries by said etching step.
A process for forming a stacked capacitor having a texturized storage node cell plate in a semiconductor integrated memory circuit fabricated on a silicon wafer, comprising the following steps:
- a) depositing a first layer of polycrystalline silicon, said first polycrystalline silicon conforming to existing topography of said silicon wafer;
- b) depositing a metal silicide superjacent said first polycrystalline silicon layer;
- c) annealing said metal silicide thereby forming silicide grain size being approximately 1/10 the size of the capacitor's storage node plate and silicon rich grain boundaries in said metal silicide film;
- d) oxidizing said metal silicide film thereby consuming silicon atoms int he grain boundaries of said metal silicide film;
- e) etching said oxide from top of said metal silicide thereby creating said texturized surface of said metal silicide;
- wherein said oxidizing step "d" and said etching step "e" are performed separately in order to first isolate said silicon atoms in the grain boundaries by said oxidizing step and then consume said oxidized silicon in the grain boundaries by said etching step;
- f) patterning and etching said metal silicide and aid first polycrystalline silicon layer thereby forming said texturized storage node cell plate;
- g) depositing a conformal layer of cell dielectric superjacent said storage node cell plate;
- and
- h) depositing a second conformal layer of polycrystalline silicon superjacent said cell dielectric, said second polycrystalline layer forming a top cell plate of said stacked capacitor.
Dependencies are inferred from the claim text.