Process for manufacturing a DMOS transistor

A method for manufacturing a semiconductor device on a wafer, comprising the steps of:

• forming a first layer of a first conductivity type on a main face of said wafer;
• forming over said first layer and insulating therefrom a gate conductive layer having a predetermined pattern defining an opening having a sidewall;
• forming a well of a second conductivity type in said main face of said first layer using said gate conductive layer as a mask;
• forming a first surface region of said first conductivity type within said well using said gate conductive layer as a mask;
• forming a sacrificial sidewall layer having a predetermined thickness over said sidewall of said gate conductive layer, said sacrificial sidewall layer substantially narrowing said opening in said gate conductive layer;
• forming a subsurface region of said second conductivity type within said well being substantially self-aligned to said sacrificial sidewall layer;
• forming a second surface region of a second conductivity type in said first surface region and having substantially higher conductivity than said subsurface region, said second surface region having a substantially narrower width than that of said first surface region and being completely surrounded by said first surface region at said face of said wafer;
• removing said sacrificial sidewall layer;
• forming an insulating sidewall over said sidewall of said gate conductive layer and having a predetermined thickness less than that of said removed sacrificial sidewall layer, so that said second surface region as well as said first surface region surrounding said second surface region are exposed;
• and
• forming a source electrode contacting said exposed first and second surface regions.

A method for making a semiconductor device at a face of a semiconductor layer, comprising the steps of:

• forming a gate over said semiconductor layer, said gate defining a through-opening to said semiconductor layer;
• forming a first region of a first conductivity type substantially self-aligned with said through-opening;
• after forming said gate, and prior to said step of forming said first region, implanting a deep well into said semiconductor layer through said through-opening;
• forming a sacrificial sidewall in said through-opening subsequent to forming said first region;
• forming a second region of a second conductivity type different than said first conductivity type substantially self-aligned with said sacrificial sidewall subsequent to forming said sacrificial sidewall;
• prior to forming said second region of said second conductivity type, forming a third region of said second conductivity type below said first region substantially self-aligned with said sacrificial sidewall;
• removing said sacrificial sidewall;
• and
• forming a high conductivity surface region in contact with both said first and second regions of said first and second conductivity type.