Threshold level generator
AssigneeRaytheon Company
InventorRobert H. Cantwell
Life of this patent
Estimating the term…
Abstract
A threshold level generator for generating threshold levels to detect zero-crossings of a spread spectrum received waveform. An IF sampler quantizes the received spread spectrum signals at IF. The IF signal is sampled at a number of quarter cycle intervals to allow sampling in sequence of the in-phase (I) and quadrature-phase (Q) components. The outputs of the IF sampler are two bits, a sign bit and a magnitude bit. The threshold level generator using only the sign bit of the I and Q samples sets a threshold level (T0) to detect the zero-crossings of a received waveform. Two magnitude threshold levels are set at fixed offsets (D1 and D2) from the T0 threshold level.
Claims3
A threshold level generator for a spread spectrum signal detector comprising:
- first register means for storing a sign bit sample of an in-phase (I) component of a carrier signal in accordance with a clock signal;
- first up/down counter means coupled to said first register means for counting up or down as determined by a logic level of the I component sign bit sample stored in said first register means;
- second register means coupled to an output of said first register means for storing said I component sign bit sample in accordance with said clock signal one-half clock period later for underflow and overflow control of said first up/down counter means;
- a set output of said second register is coupled to a least significant bit of said first up/down counter means and a reset output of said second register is coupled to most significant bits of said first up/down counter means for providing continuous operation of said first up/down counter means during overflow and underflow conditions;
- third register means coupled to the output of said first up/down counter means for storing an output of said first up/down counter means;
- fourth register means for storing a sign bit sample of a quadrature-phase (Q) component of said carrier signal in accordance with said clock signal;
- second up/down counter means coupled to said fourth register means for counting up or down as determined by a logic level of the Q component sign bit sample stored in said fourth register means;
- fifth register means coupled to an output of said fourth register means for storing said Q component sign bit sample in accordance with said clock signal one-half clock period later for underflow and overflow control of said second up/down counter means;
- a set output of said fifth register is coupled to a least significant bit of said second up/down counter means and a reset output of said fifth register is coupled to ten most significant bits of said second up/down counter means for providing continuous operation of said second up/down counter means during overflow and underflow conditions;
- sixth register means coupled to the output of said second up/down counter means for storing an output of said second up/down counter means;
- adder means coupled to the outputs of said third register means and said sixth register means for determining a sum of the outputs of said first up/down counter means and said second up/down counter means;
- and
- digital to analog converter means for converting said sum to a zero-mean threshold level (T0).
Dependencies are inferred from the claim text.