Short circuit detector circuit for memory arrays

A circuit for detecting short circuits in a static random access memory, said memory comprising a plurality of memory cells, each memory cell having a row select input coupled to a row select line and a connection to a power supply, said memory cells arranged in rows and all memory cells in a common row coupled to the same row select line by said row select inputs, said circuit comprising:

• first transistor means having their sources connected to said power supply and their gates connected individually to successive row select lines;
• second transistor means having their sources connected to the drain of said first transistor means, their gates coupled to said power supply, and their drains connected to a current sense line;
• and
• current sensing circuit means, for detecting when current flows through said current sense line;
• computer means for selecting one of said row select lines and for activating said current sensing circuit means so that an improper voltage level on the gate of said second transistor means permits current to flow on said current sense line.

A circuit for detecting voltage supply short circuits in an array of static random access memory cells, said cells being arranged in rows and each row selectable in response to a signal on a row select line, said cells having a memory matrix voltage supply derived from an external power supply, said circuit comprising:

• a first and second transistor, for each row of said cells, coupled in a series, the gates of said first and second transistor coupled respectively to said row select line and to said memory matrix voltage supply, the source of said first transistor coupled to said external power supply, and the drain of said first transistor coupled to the source of said second transistor;
• a current sense line coupled to the drain of said second transistor;
• a current detector circuit coupled to said current sense line for generating a logic output signal in response to current flow along said current sense line;
• and
• means for selectively biasing each of said first transistor sin a conductive state and for activating said detector circuit such that in response to an improper voltage on said memory matrix voltage supply corresponding when the voltage at said second circuit node rises above a predefined value;
• an encoding circuit means for encoding information identifying said array of static random access memory cells coupled in parallel with said first transistor for each row of said cells.