Built-in test circuitry providing simple and accurate AC test of digital microcircuits with low bandwidth test equipment and probe stations

A test circuit for speed testing data propagation paths of an integrated circuit device having a clock buffer and wherein each data propagation path includes (i) a combinatorial logic network or (ii) N combinatorial logic networks and N-1 scan registers interposed between individual ones of the N combinatorial logic networks, the test circuit for comprising:

• a plurality of input scan registers for the plurality of data propagation paths for providing input data for the respective data propagation paths;
• and
• a plurality of output scan registers for storing the outputs of the respective data propagation paths;
• wherein said input and output scan registers and any internal scan registers in the data propagation paths are (a) serially operated pursuant to a first clock that can have an arbitrarily long period to serially scan in test values, (b) subsequently operated in parallel pursuant to active clock transitions at the start and end of a cycle of a second clock having a period that corresponds to a desired test speed, and (c) serially operated pursuant to the first clock to serially scan out test result values, whereby test values are applied to, and sampled from, the combinatorial logic networks at the rate of the second clock so as to test whether the delays through the combinatorial logic networks are less than or equal to the second clock period.

In an integrated circuit having (a) a clock buffer, (b) a plurality of data propagation paths respectively (i) a combinatorial logic network or (ii) N combinatorial logic networks and N-1 registers interposed between individual ones of the N combinatorial logic networks, (c) a plurality of input latches for the plurality of data propagation paths for receiving test data from the automatic test equipment and for providing respective input data for the associated data propagation paths, and (d) a plurality of output latches for respectively storing the outputs of the respective data propagation paths, a method for speed testing the data propagation paths comprising the steps of:

• (A) clocking the input and output latches and any internal registers in the data propagation paths alternating single cycles of a first clock that can be arbitrarily slow and a second clock that corresponds to a desired test speed;
• (B) transferring data between the automatic test equipment and the input latches pursuant to the first clock;
• (C) transferring data between the input latch and the data propagation path pursuant to the second clock, and transferring data between the output of the data propagation paths and the associated output latches pursuant to second clock;
• (D) transferring data between the output latches and the automatic test equipment pursuant to the first clock;
• whereby any internal registers in the data propagation path and said output storage means are subjected to active clock transitions at the start and end of each cycle of said second clock such that test data is applied to, and sampled from, the combinatorial logic networks at the rate of the second clock, so as to test whether the delays through the combinatorial logic networks are less than or equal to the period of said second clock.

In an integrated circuit device having (a) a clock buffer, (b) a plurality of data propagation paths respectively including (i) a combinatorial logic network or (ii) N combinatorial logic networks and N-1 scan registers interposed between individual ones of the N combinatorial logic networks, (c) a plurality of input scan registers for the plurality of data propagation paths for providing input data for the respective data propagation paths, and (d) a plurality of output scan registers for storing the outputs of the respective data propagation paths, a method for speed testing the data propagation paths comprising the steps of:

• (A) serially operating the input and output scan registers and any internal scan registers in the data propagation paths pursuant to a first clock that can have an arbitrarily long period to serially scan in test values;
• (B) subsequently operating the input and output scan registers and any internal scan registers in the data propagation paths parallel pursuant to active clock transitions at the start and end of a cycle of a second clock having a period that corresponds to a desired test speed;
• and
• (C) serially operating the input and output scan registers and any internal scan registers in the data propagation paths pursuant to the first clock to serially scan out test result values;
• whereby test values are applied to, and sampled from, the combinatorial logic networks at the rate of the second clock, which tests whether the delays through the combinatorial logic networks are less than or equal to the second clock period.

In an integrated circuit device having (a) a clock buffer, (b) a plurality of data propagation paths respectively including (i) a combinatorial logic network or (ii) N combinatorial logic networks and N-1 scan registers interposed between individual ones of the N combinatorial logic networks,, (c) a plurality of input latches for the plurality of data propagation paths for providing input data for the respective data propagation paths, and (d) a plurality of output latches for storing the outputs of the respective data propagation paths, a method for speed testing the data propagation paths comprising the steps of:

• (A) operating the internal scan registers in the data propagation paths in the serial mode pursuant a series of cycles of a first clock that can have an arbitrarily long period to serially scan in scan register test values;
• (B) operating the input latches pursuant to receive latch test values pursuant to the cycle of the first clock when the last register test value is scanned into internal scan registers;
• (C) operating the input and output latches and any the internal scan registers in the data propagation paths in parallel pursuant to active clock transitions at the start and end of a cycle of a second clock having a period that corresponds to a desired test speed;
• (D) operating the internal scan registers in the data propagation paths in the serial mode pursuant to the first clock to serially scan out test result values;
• and
• (E) operating the output latches pursuant to the first clock so that the test result values in the output latches can be read during the first cycle of the first clock utilized in step (D) to serially scan out test result values from the internal scan registers;
• whereby test values are applied to, and sampled from, the combinatorial logic networks at the rate of the second clock, so as to test whether the delays through the combinatorial logic networks are less than or equal to the second clock period.