Semiconductor memory device

A semiconductor memory device comprising:

• a plurality of memory cells each of which including volatile memory means having a capacitor means, non-volatile memory means having a floating gate transistor, and switch means for transferring data between said volatile memory means and said non-volatile memory means;
• and a plurality of bit lines to which said memory cells are connected;
• a plurality of word lines which function as word electrodes common to said memory cells,
• the control gate of said floating gate transistor being connected to the electrode of said capacitor means, said electrode being connected to said switch means,
• said device further comprising:
• means for setting a voltage potential of a power source of said floating gate transistor to ground level when data stored in said non-volatile memory means is to be transferred to said volatile memory means;
• and
• means for setting the potential of one of said bit lines forming a bit line pair to which one the selected memory cell is connected to the power source level when data stored in said non-volatile memory means is to be transferred to said volatile memory means, and, after setting the potential of the other bit line to an intermediate potential, connecting said non-volatile memory means to said bit line, and thereafter, electrically separating said non-volatile memory means from said bit line, and amplifying the potential difference between said bit line pair.

In a semiconductor memory device comprising:

• a plurality of memory cells each of which including volatile memory means having a capacitor means, non-volatile memory means having a floating gate transistor, and switch means for transferring data between said volatile memory means and said non-volatile memory means;
• and a plurality of bit lines to which said memory cells are connected;
• a plurality of word lines portions of which function as word electrodes common to said memory cells,
• the control gate of said floating gate transistor being connected to an electrode of said capacitor means, said electrode being connected to said switch means,
• said device further comprising:
• means for setting a voltage potential of a power source of said floating gate transistor to a ground level when data stored in said non-volatile memory means is to be transferred to said volatile memory means;
• and
• a means for setting a potential of all of said volatile means to the power source level when data stored in said non-volatile memory means is to be transferred to said volatile memory means, and thereafter setting said switch means to an on condition.

A semiconductor memory device comprising:

• memory cells having volatile memory means, non-volatile memory means and switch means said switch means being conductive during recall operation;
• bit line pairs connected to said memory cells;
• a pullup transistor drive control signal line;
• sense amplifiers having a p-channel MOS transistor connected between said bit line pairs and said pullup transistor drive control signal line;
• a bit line charging circuit for, before recall operation, charging said bit line pairs to an intermediate potential which is between a power source level and ground level, and thereafter charging the bit line to which the selected memory cell is connected to the power source level;
• and
• a sense amplifier drive circuit for lowering the potential of said bit line from the power source level to the intermediate potential plus the threshold voltage of said p-channel MOS transistor.

A semiconductor memory device comprising:

• memory cells having a volatile memory means, a non-volatile memory means and a switch means which is conductive during a memory recall operation;
• bit line pairs connected to said memory cells;
• a pullup transistor drive control signal line;
• a pulldown transistor drive control signal line;
• a sense amplifier drive circuit for, before recall operation, charging said pullup transistor drive control signal line and said pulldown transistor drive control signal line to an intermediate potential;
• and
• a bit line charging circuit for, before recall operation, charging said bit line pairs to an intermediate potential which is between a power source level and the ground level, and thereafter charging the bit line to which the selected memory cell is connected to the power source level;
• and
• sense amplifiers having:
• a pair of pullup p-channel MOS transistors one terminal of which is connected to said pullup transistor drive control signal line;
• a pair of pulldown n-channel MOS transistors one terminal of which is connected to said pulldown transistor drive control signal line;
• and a pair of separation p-channel MOS transistors which is connected between other terminals of said pullup transistor drive control signal line and pulldown transistor drive control signal line, the junctions of said separation p-channel MOS transistors and pulldown n-channel MOS transistors being respectively connected to said bit line pairs.