Parallel multiplier using skip array and modified wallace tree
AssigneeSamsumg Electronics Co., Ltd.
InventorsTack D. Han, Sang M. Moh
Life of this patent
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Abstract
A parallel multiplier by a skip array and a modified Wallace tree utilizes a modified Booth's encoder for encoding a multiplier according to a modified Booth's algorithm, a skip array for partial products, a modified wallace tree for adding binary bits, and a hybrid prefix adder for adding the final two lines. Fast multiplication of 0 (log n) is continuously performed without a standby state of a carry output and the regularity of the arrangement of the parallel multiplier is improved so that its chip area and manufacturing cost are reduced.
Claims7
A parallel multiplier using a skip array and a modified Wallace tree, comprising:
- a modified Booth's encoder for receiving an n-bit multiplier signal and calculating bit-respective (3 *(n/2)) encoded output signals, wherein n represents respective bits of the multiplier signal, according to a modified Booth's algorithm;
- a skip array for receiving an n-bit multiplicand signal and having input lines for respectively receiving the encoded output signals and output lines, the skip array calculating a reduced number of n/log (n/2) partial products from the multiplicand and encoded output signals;
- a modified Wallace tree for adding binary bits of the partial products in full adders for providing a final carry output signal and a final sum output signal;
- and
- a hybrid prefix adder for adding the final carry output and sum output signals.
Dependencies are inferred from the claim text.