Apparatus for multiplying real-time 2's complement code in a digital signal processing system and a method for the same
AssigneeSamsung Electronics Co., Ltd.
InventorsDae-Yoon Shim, Jong-Sang Lim
Life of this patent
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Abstract
A pipeline multiplier capable of multiplying 2's complement codes is disclosed. The multiplier operates the multiplication faster than the conventional one by receiving a first predetermined-bit of a multiplier and a second predetermined-bit of multiplicand; producing a multiplier multiplied by sequentially from a least significant bit (LSB) for the times of the second predetermined-bit numbers; logically ORing a most significant bit (MSB) of a preceding partial sum with a MSB of a present partial sum so as to correct the partial sums; and subtracting output of a last partial sum from a value produced by logically NANDing the multiplier and the MSB of the second predetermined-bit of the multiplicand.
Claims12
A pipeline multiplier, capable of multiplying 2's complement codes, said pipeline multiplier comprising:
- a plurality of serially connected partial sum generating means each receiving preceding partial sums and generating present partials sums;
- partial sum correcting means for sequentially receiving bits comprising a multiplier and a multiplicand, producing first values by sequentially multiplying said bits by said multiplicand, in logic circuits, and logically combining, in first logic gate circuits, a most significant bit of preceding partial sums with a most significant bit of said first values so as to correct present partial sums;
- and
- a 2's complement correcting means for subtracting a present partial sum generated by a last one of said plurality of serially connected partial sum generating means from a second value produced by logically combining, in a second logic gate circuit, said multiplicand with the most significant bit of said multiplier.
A pipeline multiplier having a plurality of latch circuits and adders, and including means for multiplying 2's complement codes, comprising a plurality of serially connected partial sum generating means, a first one of said plurality of serially connected partial sum generating means comprising:
- first latch means for receiving a multiplicand;
- second latch means for receiving a multiplier and for providing a least significant bit and a next significant bit of said multiplier,
- first means and second means for respectively combining said least significant bit and said next significant bit with said multiplicand;
- an adder for producing a present partial sum from the outputs of said first combining means and said second combining means;
- gate means for producing a correction signal from a most significant bit of said output of said first combining means with a most significant bit of said output of said second combining means;
- and
- partial sum correcting means for receiving said present partial sum and said correction signal and generating a corrected partial sum.
A pipeline multiplier having a plurality of latch circuits and adders, and including means for multiplying 2's complement codes, and having a plurality of stages for producing a sequence of partial sums, at least one of said plurality of stages comprising:
- first latch means for receiving a multiplicand;
- second latch means for receiving a multiplier and for providing a selected bit of said multiplier, said selected bit being for each of said plurality of stages;
- AND gate means for combining said selected bit with said multiplicand to generate a value;
- an adder for producing a present partial sum by adding said value to a preceding partial sum generated by a preceding one of said plurality of states;
- OR gate means for producing a correction signal from the most significant bit of said value and the most significant bit of said preceding partial sum;
- and
- partial sum correcting means for receiving said present partial sum and said correction signal to generate a corrected partial sum.
A pipeline multiplier capable of multiplying two numbers each in 2's complement format, said pipeline multiplier comprising:
- a plurality of serially connected partial sum generating means, each comprising a first latch, a second latch, and an adder for sequentially generating partial sums by adding, in said adder, preceding partial sums received from said first latch to a multiplier received from said second latch multiplied by a selected bit of bits comprising said multiplicand, said selected bit being different for each of said plurality of serially connected partial sum generating means;
- a plurality of partial sum correcting means each associated with a different one of said plurality of serially connected partial sum generating means for correcting partial sums by logically combining, in logic gate circuits, a most significant bit of said preceding partials sum with a most significant bit of said multiplier multiplied by said selected bit;
- and
- 2's compliment correcting means for subtracting a last partial sum generated by a last one of said plurality of serially connected partial sum generating means from a value produced by logically combining said multiplier and a most significant bit of said multiplicand.
A method for multiplying two 2's complement numbers in a pipeline multiplier by sequentially adding partial sums, at least one of said partial sums determined by a method comprising:
- receiving a preceding partial sum and latching said preceding partial sum in a latch;
- multiplying, in a first logic gate circuit, a bit of a multiplier selected from bits comprising said multiplier by a multiplicand to generate a value, said bit selected depending on which of sad partial sums is being calculated;
- generating a correction bit by logically combining, in a second logic gate circuit, a most significant bit of said preceding partial sum with a most significant bit of said value;
- and
- generating a corrected partial sum by latching said correction bit and the result of adding said value to said preceding partial sum.
Dependencies are inferred from the claim text.