Discrete cosine transform circuit suitable for integrated circuit implementation

A DCT circuit for performing DCT or IDCT with N (N=2.sup.x where x is a natural number) input data in response to a selection signal fed from the outside so as to produce transformed data, said DCT circuit comprising:

• (a) first switch means for producing first selected input data by selecting, in response to the selection signal, either one of input data and selected accumulation data produced in said DCT circuit;
• (b) combining circuit means for transforming N of said first selected input data into N/2 combination data each comprising a combination of two predetermined data;
• (c) adding and subtracting means for producing N subtraction and addition data by adding first and second data of each of said combination data and subtracting said second data from said first data;
• (d) second switch means for producing second selected input data by selecting, in response to the selection signal, either one of said input data and said selected accumulation data;
• (e) permutation circuit means for outputting permutated data by permutating N of said second selected input data in a predetermined order;
• (f) third switch means for outputting data to be transformed by selecting, in response to the selection signal, one of said input data, said addition and subtraction data and said permutated data;
• (g) N/2 transforming circuit means for transforming data having an identical construction, m-th (2.ltoreq.m.ltoreq.N/2 where m is an integer) one of said N/2 transforming circuit means comprising:
• (i) coefficient memory means storing DCT coefficients, IDCT coefficients, and filter coefficients;
• (ii) multiplier means for reading, in response to the selection signal, one of said DCT coefficients, said IDCT coefficients and said filter coefficients out of said memory means and multiplying said data to be transformed by said coefficients to produce multiplication data;
• (iii) adder means for adding said multiplication data and locally accumulated data to output updated accumulation data;
• (iv) first selector means for selecting, in response to the selection signal, either one of said updated accumulation data and said updated accumulation data in the (m-l)-th transforming circuit means to output said locally accumulated data;
• and
• (v) register means for outputting said updated accumulation data at a predetermined period as accumulation data;
• (h) first one of said N/2 transforming circuit means comprising:
• (i) coefficient memory means storing DCT coefficients, IDCT coefficients, and filter coefficients;
• (ii) multiplier means for reading, in response to the selection signal, one of said DCT coefficients, said IDCT coefficients and said filter coefficients out of said memory means and multiplying said data to be transformed by said coefficients to produce multiplication data;
• (iii) adder means for adding said multiplication data and locally accumulated data to output updated accumulation data;
• and
• (iv) register means for accumulating said updated accumulation data at a predetermined period to output accumulation data;
• (i) fourth switching means for selecting, in response to the selection signal, one of said updated accumulation data from the N/2-th transforming circuit means, said permutated data, and said subtraction and addition data to output said transformed data;
• and
• (j) selector means for selecting said accumulation data from said N/2 transforming circuit means in a predetermined order and feeding said selected accumulation data to said first and second switch means as said selected accumulation data.

A DCT circuit for performing DCT with N one-dimensional data (N=2.sup.x where x is a natural number), comprising:

• (a) combining circuit means for transforming each N input data into N/2 combination data each consisting of two predetermined data, and outputting first and second data constituting each of said combination data in parallel;
• (b) first adder means for producing first addition data by adding said first and second data;
• (c) subtractor means for producing substraction data by subtracting said second data from said first data;
• (d) N transforming circuit means for transforming data having an identical construction and each comprising:
• (i) coefficient memory means storing DCT coefficients;
• (ii) multiplier means for multiplying data to be transformed by said DCT coefficients read out of said coefficient memory to output multiplication data;
• (iii) second adder means for adding said multiplication data and locally accumulated data to output second addition data;
• and
• (iv) register means for outputting said second addition data as said locally accumulated data and outputting, at a predetermined period, said second addition data as accumulation data;
• (e) distributing means for feeding said first addition data to, among said N transforming circuit means, N/2 transforming circuit means as said data to be transformed and feeding said subtraction data as said data to be transformed to the other N/2 transforming circuit means;
• and
• (f) selector means for outputting said accumulation data from said N transforming circuit means in a predetermined order as a DCT result of said input data.

An IDCT circuit for performing IDCT with N (N=2.sup.x where x is a natural number) one-dimensional transformed data resulted from DCT of N one-dimensional data, comprising:

• (a) combining circuit means for transforming said N transformed data into N/2 combination data each consisting of two predetermined data, and outputting first and second data constituting each of said combination data in parallel;
• (b) N transforming circuit means for transforming data having an identical construction and each comprising:
• (i) coefficient memory means storing DCT coefficients;
• (ii) multiplier means for multiplying data to be transformed by said DCT coefficients read out of said coefficient memory to output multiplication data;
• (iii) first adder means for adding said multiplication data and locally accumulated data to output first addition data;
• and
• (iv) register means for outputting said first addition data as said locally accumulated data and outputting, at a predetermined period, said first addition data as accumulation data;
• (c) distributing means for feeding said first addition data to, among said N transforming circuit means, N/2 transforming circuit means as said data to be transformed and feeding second addition data as said data to be transformed to the other N/2 transforming circuit means;
• (d) first selector means for outputting said accumulation data from said N/2 transforming circuit means in a predetermined order as first selected accumulation data;
• (e) second selector means for outputting said accumulation data from said other N/2 transforming circuit means in a predetermined order as second selected accumulation data;
• (f) second adder means for adding said first and second selected accumulation data to output second addition data;
• (g) subtractor means for subtracting said second selected accumulation data from said first selected accumulation data to output substraction data;
• and
• (h) permutating circuit means for outputting said second addition data and said subtraction data after permutating said data in a predetermined order.

A DCT circuit for performing N-degree (N=2.sup.x where x is a natural number) DCT or IDCT in response to a selection signal fed from the outside, said DCT circuit comprising:

• (a) first combining circuit means for transforming, according to a predetermined first combination, each N input data into first N/2 combination data each consisting of two predetermined data, and outputting first and second data constituting each of said combination data in parallel;
• (b) first adder means for adding said first and second data to produce first addition data;
• (c) first subtractor means for subtracting said second data from said first data to produce first subtraction data;
• (d) second combining circuit means for transforming, according to a predetermined second combination, said each N input data into second N/2 combination data each consisting of two predetermined data, and outputting third and fourth data constituting each of said second combination data in parallel;
• (e) first selector means for selecting either one of said third data and said first addition data in response to the selection signal to output said selected data as first selected data;
• (f) second selector means for selecting either one of said fourth data and said subtraction data in response to the selection signal to output said selected data as second selected data;
• (g) N transforming circuit means for transforming data having an identical construction and each comprising:
• (i) coefficient memory means storing DCT coefficients;
• (ii) multiplier means for multiplying data to be transformed by said DCT coefficients read out of said coefficient memory to output multiplication data;
• (iii) second adder means for adding said multiplication data and locally accumulated data to output said addition data;
• and
• (iv) register means for outputting said second addition data as said locally accumulated data and outputting, at a predetermined period, said second addition data as accumulation data;
• (h) distributing means for feeding said first selected data to, among said N transforming circuit means, N/2 transforming circuit means as said data to be transformed and feeding second selected data as said data to be transformed to the other N/2 transforming circuit means;
• (i) third selector means for outputting said accumulation data from said N/2 transforming circuit means in a predetermined order as first selected accumulation data;
• (j) fourth selector means for outputting said accumulation data from said other N/2 transforming circuit means in a predetermined order as second selected accumulation data;
• (k) third adder means for adding said first and second selected accumulation data to produce third addition data;
• (l) second subtractor means for subtracting said second selected accumulation data from said first selected accumulation data to produce second subtraction data;
• and
• (m) permutation circuit means for permutating, in response to the selection signal;
• (i) said third and fourth selected data in a predetermined order to output said permutated data as a DCT result, or
• (ii) permutating said third addition data and said second subtraction data in a predetermined order to output said permutated data as an IDCT result.

A DCT circuit for performing DCT with N.times.N (N=2.sup.x where x is a natural number) input data, comprising:

• (a) first switch means for selecting and outputting, in response to a first control signal fed from the outside, either one of said input data and transposition data as data to be transformed;
• (b) a one-dimensional DCT circuit for performing N-degree one-dimensional DCT with said data to be transformed to output first transformed data;
• (c) second switch means for outputting, in response to a second control signal fed from the outside, said first transformed data via one output as a two-dimensional DCT result or via the other output as a one-dimensional DCT result;
• and
• (d) transpositioning means for transpositioning said one-dimensional DCT result to output said transpositioning data;
• wherein said one-dimensional DCT circuit further comprises:
• a plurality of registers;
• a plurality of selectors;
• a shift register receiving said input data comprising a first group of said registers electrically coupled serially to one another;
• a combining circuit for combining said input data to produce combined data, said combining circuit comprising said shift register, a second group of said registers, and first and second ones of said selectors electrically coupled to one another;
• and
• a permutation circuit for receiving and permutating said combined data, said permutation circuit comprising said shift register, a third one of said selectors and at least one other of said registers electrically coupled to one another.

A two-dimensional DCT circuit for performing N.times.N two-dimensional DCT or IDCT with N-degree (N=2.sup.x where x is a natural number) input data in response to a selection signal fed from the outside, said DCT circuit comprising:

• (a) first one-dimensional DCT/IDCT circuit means for performing, in response to the selection signal, N-degree one-dimensional DCT or N-degree one-dimensional IDCT with said input data and outputting a transform result as first transformed data;
• (b) transpositioning means for transpositioning said first transformed data to output transposition data;
• and
• (c) second DCT/IDCT circuit means for performing, in response to the selection signal, one of the N-degree one-dimensional DCT and the N-degree one-dimensional IDCT which said first DCT/IDCT circuit has performed with said input data with said transposition data, when performing the N-degree one-dimensional DCT outputting a transform result as a two-dimensional DCT result associated with said input data, and when performing the N-degree one-dimensional IDCT outputting a transform result as a two-dimensional IDCT result;
• wherein said one-dimensional DCT circuit further comprises:
• a plurality of registers;
• a plurality of selectors;
• a shift register receiving said input data, said shift register comprising a first group of said registers electrically and serially coupled to one another;
• a combining circuit for combining said input data to produced combined data, said combining circuit comprising said shift register, a second group of said registers, and first and second ones of said selectors electrically coupled to one another;
• and
• a permutation circuit for permutating said combined data, said permutation circuit comprising said shift register, a third one of said selectors and at least one other of said registers electrically coupled to one another.