Digital phase-locked loop

In a digital phase-locked loop having generating means for generating an output signal of period T, the signal representing an actual phase of the generating means by increasing a register word of length N successively by using a control word (st) which is applied at an input of the digital oscillator and at a predetermined clock rate of a clock generator:

• and processing means which is provided with the digital oscillator output signal and which performs a phase comparison between the actual phase of the generating means and a reference phase to adjust the period T of the generating means to a nominal period determined by periodically occurring synchronizing pulses, such that the processing means forms a phase-difference signal from the actual phase of the digital oscillator and from the reference phase at a first control clock rate which is determined by the periodically occurring synchronizing pulses, and such that the phase-difference signal is filtered in the processing means and is added to a frequency word (f), the frequency word (f) having a numerical value which represents the nominal period as a function of the length N of the register word of the generating means and the predetermined clock rate of the clock generator, wherein during successive accumulation of the register word by the frequency word (f), the generating means overflows in the nominal period and the control word (st), formed from the frequency word (f) and the phase-difference signal, is applied to the input of the generating means, the improvement therewith including means coupled to the processing means for generating a signal sequence with a one-half line period and for being locked to the digital oscillator output signal, said signal sequence having a period TD equal to one-half the period T of the output signal, such that after the generating means is locked to the nominal period, the processing means performs the phase comparison between the actual and reference phases with the signal sequence being of one-half line period and at a second control clock rate, which is determined by line-periodic synchronizing pulses and a non-line periodic synchronizing pulse, and correcting means for correcting an address-phase signal, and having applied thereto said output signal and said signal sequence, said address-phase signal being locked to the output signal such that in the presence of a non-periodic synchronizing pulse, an address phase of the address-phase signal is shifted by the period TD of the signal sequence having one-half line period with respect to the phase of the output signal.