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US 5,181,091 AGranted
Integrated circuit with improved protection against negative transients
AssigneeDallas Semiconductor Corporation
InventorsThomas E. Harrington, III, Robert D. Lee
Life of this patent
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Abstract
A battery-backed integrated circuit, with a double diode structure connected to signal lines. In the double diode structure, a first junction is three-dimensionally enclosed by a second junction, so that minority carriers generated at the first junction will be collected at the second junction. Thus, when a negative transient voltage appears on the signal line, the first junction can be forward biassed to source the needed current from ground, with minimal minority carrier injection.
Claims19
An output protection structure for CMOS integrated circuit, comprising:
- at least one signal output terminal, said signal output terminal being connected to be driven by a driver field effect transistor formed in a semiconductor layer;
- a first region in said layer having a first conductivity type, and connected to ground potential;
- said first region abutting a second region having a second conductivity type which is opposite to said first conductivity type, said first and second regions defining a first junction therebetween;
- said second region being connected to said signal terminal so that said first junction will be forward biased if said signal output terminal is pulled negative by an externally applied voltage;
- a second junction surrounding said first junction, said second junction being shorted out by an ohmic connection;
- whereby minority carriers which are injected in the vicinity of said first junction will be collected at said second junction.
3 more elements
An integrated circuit, comprising:
- at least one signal output terminal, said signal output terminal being connected to be driven by a driver field effect transistor;
- an extended region of P-type monocrystalline semiconductor material connected to ground potential;
- at least one N-well region within said extended region, and at least one P-channel field-effect transistor formed in said N-well region;
- at least one N-channel field effect transistor formed in portions of said extended region;
- said signal output terminal being connected to ground potential through an isolating structure which includes:
- a first region which is P-type;
- a second region which is N-type, which is ohmically connected to said signal terminal, and which is surrounded by said first region;
- said first and second regions defining a first junction therebetween;
- a third region which is N-type and which surrounds said first region, said first and third regions defining a second junction therebetween;
- said first and third regions being ohmically connected to each other and to ground;
- whereby minority carriers which are injected in the vicinity of said first junction will be collected at said second junction.
8 more elements
Dependencies are inferred from the claim text.