High voltage CMOS devices

In a semiconductor device comprising a substrate having a memory cell region and a peripheral circuit region, the memory cell region being composed of a plurality of memory transistors each defined by a first high breakdown voltage transistor of a first conductivity type and a plurality of select transistors each defined by a second high breakdown voltage transistor of the first conductivity type, and the peripheral circuit region having a part which is constituted by a third high breakdown voltage transistor of a second conductivity type, the improvement wherein:

• said first and second high breakdown voltage transistors each include a first gate electrode having an end, and a first offset region defined by a low concentration impurity region having a substantially flat surface which is formed in a region of said substrate which is below and adjacent to said end of said first gate electrode;
• and said third high breakdown voltage transistor has a second gate electrode, a thick insulating film provided at one side of said second gate electrode, with at least a part of said film being buried in said substrate, and a second offset region defined by a low concentration impurity region provided in a region of said substrate which is under said thick insulating film.