Semiconductor device and method of producing the same

A semiconductor device comprising:

• a semi-insulating GaAs substrate;
• an undoped GaAs or Al.sub.y Ga.sub.1-y As layer, the value of y ranging from 0.3 to 0.4;
• a doped GaAs layer;
• and
• another undoped Al.sub.z Ga.sub.1-z As layer, the value z ranging from 0.3 to 0.4;
• said layers and substrate being positionally disposed in a vertically stacking arrangement and in the order given above, and further comprising:
• a cap layer of high impurity concentration disposed on said another undoped Al.sub.z Ga.sub.1-z As layer and having a recess for forming a gate electrode therethrough;
• said gate electrode being disposed inside said recess and on said another undoped Al.sub.z Ga.sub.1-z As layer;
• a source electrode disposed on said cap layer;
• and
• a drain electrode disposed on said cap layer,
• wherein said cap layer is composed of Ge having a dopant impurity concentration of about 10.sup.20 cm.sup.-3 and a thickness of about 500.ANG. or more,
• wherein said cap layer and said another undoped Al.sub.z G.sub.1-z As layer form a hetero-junction between them, and
• wherein said source electrode and said drain electrode are disposed so as to lie predetermined distances respectively away from the periphery of said recess.

A semiconductor device of FET type comprising:

• an undoped GaAs layer;
• an n-type AlGaAs layer;
• a doped n-type GaAs cap layer, said layers being positionally disposed in a vertically contacting arrangement in the order given;
• wherein a 2-dimensional electron gas layer is formed in said undoped GaAs layer in the vicinity of the interface between said AlGaAs layer and said undoped GaAs layer;
• wherein said doped n-type GaAs cap layer has a thickness of about 1600.ANG. or more and said cap layer has a recess for forming a gate electrode therethrough;
• wherein a source electrode and a drain electrode are dispose don said n-type GaAs cap layer;
• and
• wherein said gate electrode is disposed inside said recess and on said n-type AlGaAs layer and isolated from said cap layer through an inorganic side wall insulator film disposed only on the side walls inside said recess in said cap layer.

A semiconductor device constructing a 2-dimensional carrier gas FET comprising:

• a first semiconductor layer being comprised of a first semiconductor having a first bandgap;
• a second semiconductor layer of a first conductivity type being disposed on said first semiconductor layer and being comprised of a second semiconductor having a second bandgap said second bandgap being greater than said first bandgap, whereby said 2-dimensional carrier gas is formed in aid first layer;
• a third semiconductor layer of low impurity concentration which has a thickness of 50-200.ANG. and which is formed between said second semiconductor layer and a Schottky gate electrode, wherein said third semiconductor layer is provided for increasing the breakdown voltage of a Schottky junction, which junction is effected by said Schottky gate electrode being formed on said third semiconductor layer;
• a fourth semiconductor layer of high impurity concentration being disposed on said third semiconductor layer and having a recess for forming therethrough said Schottky gate electrode, wherein said Schottky gate electrode is disposed inside said recess and on said third semiconductor layer and isolated from said fourth semiconductor layer through an inorganic side wall insulator film disposed on the side walls inside said recess in said fourth semiconductor layer, and wherein said fourth semiconductor layer is of a first conductivity type;
• a source electrode being disposed on said fourth semiconductor layer;
• and
• a drain electrode being disposed on said fourth semiconductor layer.

A semiconductor device constructing a 2-dimensional carrier gas FET comprising:

• a first semiconductor layer being comprised of a first semiconductor having a first bandgap;
• a second semiconductor layer being comprised of a second semiconductor having a second bandgap and being of a first conductivity type, said second bandgap being greater than said first bandgap, whereby said 2-dimensional carrier gas is formed in said first layer;
• a third semiconductor layer or high impurity concentration disposed on said second semiconductor layer and having a recess for forming therethrough a Schottky gate electrode, whereby said third semiconductor layer forms a heterojunction with that portion of said second semiconductor layer disposed beneath said third semiconductor layer, and wherein said third semiconductor layer is of a first conductivity type;
• a Schottky gate electrode being disposed inside said recess and on said second semiconductor layer and isolated from said third semiconductor layer through an inorganic side wall insulator film disposed only on the side walls inside said recess in said third semiconductor layer;
• a source electrode being disposed on said third semiconductor layer;
• a drain electrode being disposed on said third semiconductor layer;
• and
• wherein said third semiconductor layer reduces the parasitic resistance between said source electrode and said gate electrode.

A semiconductor device comprising:

• a first semiconductor layer having a first bandgap and being of a first conductivity type, whereby said first semiconductor layer provides a channel for said semiconductor device;
• a second semiconductor layer of low impurity concentration having a thickness of 50-200.ANG. and a second bandgap, said second bandgap being greater than said first bandgap and said second semiconductor layer having formed thereon a Schottky gate electrode, wherein said second semiconductor layer is provided for increasing the breakdown voltage of a Schottky junction, which junction is effected by said Schottky gate electrode being formed on said second semiconductor layer;
• a third semiconductor layer of high impurity concentration being disposed on said second semiconductor layer and having a recess for forming therethrough said Schottky gate electrode, said Schottky gate electrode being disposed inside said recess and on said second semiconductor layer and isolated from said third semiconductor layer through an inorganic side wall insulator film disposed only on the side walls inside said recess in said third semiconductor layer, whereby said third semiconductor layer forms a heterojunction with that portion of said second semiconductor layer disposed beneath said third semiconductor layer, wherein said third semiconductor layer reduces the parasitic resistance between a source electrode and a gate electrode, and wherein said third semiconductor layer is of a first conductivity type;
• a source electrode being disposed on said third semiconductor layer;
• and
• a drain electrode being disposed on said third semiconductor layer.

A semiconductor device comprising:

• a plurality of vertically stacked semiconductor layers, wherein one of which includes a channel region;
• a pair of electrodes electrically connected to said channel region;
• and
• gate means for controlling current flowing in said channel region,
• wherein another one of said semiconductor layers includes a pair of low-resistivity semiconductor cap regions which form a heterojunction with a different compound type semiconductor region corresponding to a still further one of said semiconductor layers, the cap regions are disposed between said channel region and the electrodes, respectively, and have formed therethrough a recessed gate structure so as to lower parasitic resistance between said gate means and the electrodes, wherein said different compound type semiconductor region is an undoped compound semiconductor region, and wherein said cap regions are respectively isolated from said gate means through an inorganic side wall insulator film disposed on the side walls inside the recess.

A semiconductor device comprising:

• a plurality of vertically stacked semiconductor layers, wherein one of said semiconductor layers is a channel region which includes a two-dimensional carrier gas;
• a pair of electrodes electrically connected to said channel region;
• and
• gate means for controlling current flowing in said channel region,
• wherein another one of said semiconductor layers includes a pair of low-resistivity semiconductor cap regions which form a heterojunction with a different compound type semiconductor region corresponding to a still further one of said semiconductor layers, the cap regions are disposed between said channel region and the electrodes, respectively, and have formed therethrough a recessed gate structure so as to lower parasitic resistance between said gate means and the electrodes, and wherein said cap regions are respectively isolated from said gate means through an inorganic side wall insulator film disposed on the side walls inside the recess.