Digital filter for filtering and decimating delta sigma modulator output signals

An analog-to-digital converter including a delta sigma modulator for receiving an analog input signal and producing a bit-rate signal, said delta sigma modulator comprising:

• differential summing means for subtracting a feedback analog signal from said analog input signal to produce a differential output signal;
• integration means for integrating said differential output signal;
• single bit analog-to-digital converter means for converting said integrated differential output signal to said bit-rate signal;
• single bit digital-to-analog converter means coupled to said single bit analog-to-digital converter means for converting said bit-rate signal to said feedback analog signal;
• a digital filter/decimator coupled to said single bit analog-to-digital converter means for filtering said bit-rate signal;
• filter characteristic control means for selecting an arbitrary predetermined filter impulse response coefficient as a binary bit;
• clock means for generating clock signals defining a clock cycle and a computation cycle;
• and
• a plurality of bit-slice filter elements coupled in cascade and forming an accumulator for providing a binary output signal for said digital filter/decimator, each bit-slice element being responsive to said bit-rate signal and said binary bit from said filter characteristic control means, and each bit-slice element comprising:
• multiplier means for multiplying said bit-rate signal and a binary bit input signal from said filter characteristic control means;
• adder means for receiving a selected output signal from said multiplier means, a signal representing a previous accumulation result for said each bit-slice element, and a carry output signal from a preceding bit-slice element, for generating a carry output signal and an accumulation result output signal;
• delay means coupled to receive said accumulation result output signal and responsive to said clock signals for delaying said accumulation result output signal by one clock cycle;
• and
• reset means responsive to said clock means for providing said previous accumulation result to said adder means and for clearing said accumulator and setting an initial condition upon termination of each computation cycle.