DC-to-AC symmetrical sine wave generator
AssigneeNEC Corporation Of America
InventorRolf H. G. Wendt
Life of this patent
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Abstract
Many electronic systems such as telephone systems require highly accurate DC-to-AC signal generators such as sine wave generators. A sine wave generator according to the present invention includes a pair of multiplexers, each receiving a plurality of DC voltages from a voltage divider network and having a common output in a summing circuit to produce a sine wave at a predetermined frequency. The multiplexers are controlled by a single up/down counter element which drives the multiplexers to produce identical waveforms in each of the four quadrants of the sine wave. The sine wave frequency can be controlled by controlling a signal provided to the up/down counter.
Claims12
A sine wave generator including a summing circuit receiving a plurality of predetermined voltages from a voltage divider via a pair of multiplexers responsive to a plurality of parallel bit sets generated by an up/down counter, the number of said predetermined voltages corresponding to a maximum number represented by a predetermined number of bits included in a respective one of said parallel bit sets and each of said predetermined voltages being different from the remaining ones of said predetermined voltages, characterized in that said summing circuit outputs said predetermined voltages as voltages of a first polarity when said up/down counter counts from a predetermined number to a maximum number and when said up/down counter counts from said maximum number to said predetermined number and said summing circuit outputs said predetermined voltages as voltages of a second polarity when said counter counts from a minimum number to said predetermined number and when said counter counts from said predetermined number to said minimum number so as to permit said summing circuit to generate a sinusoidal signal in response to said parallel bit sets.
A sine wave generator comprising:
- an up/down counter for generating a plurality of parallel bit sets, wherein each of said parallel bit sets includes n bits where n is an integer and a most significant bit and wherein each of said parallel bit sets corresponds to a respective count value in a range bounded by a minimum value and a maximum value, in response to a plurality of serial bits;
- a voltage divider network generating a plurality of predetermined voltages, wherein the number of said predetermined voltages corresponds to a maximum number represented by said n bits and wherein each of said predetermined voltages is different from the remaining ones of said predetermined voltages;
- first and second multiplexers operatively coupled to said up/down counter to receive said parallel bit sets and operatively connected to said voltage divider network to receive one of said predetermined voltages in response to said n bits of a respective one of said parallel bit sets, wherein one of said first and second multiplexers is enabled while the other of said first and second multiplexers is inhibited based on said most significant bit in each of said respective parallel bit set;
- and
- a summing circuit operatively connected to said first and second multiplexers to receive said predetermined voltages in response to said parallel bits for producing first polarity voltages based on said predetermined voltages when said up/down counter counts from said minimum value to a predetermined value and from said predetermined value to said minimum value and for producing second polarity voltages based on said predetermined voltages when said up/down counter counts from said predetermined value to said maximum value and from said maximum value to said predetermined value so as to permit said summing circuit to produce a sinusoidal output signal.
A sine wave generator generating a filtered sinusoidal output signal in response to a plurality of serial bits, said sine wave generator comprising:
- an up/down counter for generating a plurality of parallel bit sets in response to the serial bits, wherein each of said parallel bit sets includes n bits where n is an integer and a most significant bit and wherein each of said parallel bit sets corresponds to a respective count value in a range bounded by a minimum value and a maximum value;
- a voltage divider network comprising a plurality of branches, each of said branches including at least one resistor, for generating a plurality of predetermined voltages, wherein the number of said predetermined voltages corresponds to a maximum number represented by said n bits and wherein each of said predetermined voltages is different from the remaining ones of said predetermined voltages;
- a first multiplexer operatively coupled to said up/down counter to receive said parallel bit sets and operatively connected to said voltage divider network to receive said predetermined voltages in a first order in response to said n bits of said parallel bit sets;
- a second multiplexer operatively coupled to said up/down counter to receive said parallel bit sets and operatively connected to said voltage divider network to receive said predetermined voltages in a second order in response to said n bits of said parallel bit sets;
- a summing circuit operatively connected to said first and second multiplexers to receive said predetermined voltages in response to said parallel bit sets for producing first polarity voltages based on said predetermined voltages when said up/down counter counts from said minimum value to a predetermined value and from said predetermined value to said minimum value and for producing second polarity voltages based on said predetermined voltages when said up/down counter counts from said predetermined value to said maximum value and from said maximum value to said predetermined value so as to permit said summing circuit to produce a sinusoidal output signal;
- and
- a filter operatively connected to said summing circuit for receiving said sinusoidal output signal and generating said filtered sinusoidal output signal;
- wherein one of said first and second multiplexers is enabled while the other of said first and second multiplexers is inhibited based on said most significant bit in each of said parallel bit sets.
Dependencies are inferred from the claim text.