Signal delay circuit having specified transistor threshold levels

Abstract

A signal delay circuit, includes a driving circuit for driving an output signal with a voltage swing between a supply voltage and a ground voltage. The signal delay circuit further includes a load capacitive means which is coupled to the output signal and has a larger value than the absolute value of the threshold voltage of the driving circuit and has a C-V characteristic curve which keeps a first capacitive value until the output voltage of the signal delay circuit reaches a first voltage and increases to a second capacitive value there and keeps the second capacitive value until the output voltage the reaches a second voltage and decreases to a third capacitive value there and keeps the third capacitive value; and which keeps a first capacitive value until the output voltage reaches a first voltage and decreases to a second capacitive value and keeps the second capacitive value until the output voltage reaches a second voltage and increases to a third capacitive value there and keeps the third capacitive value. The load capacitive means keeps the delay characteristic of the signal delay circuit independently of the change of the supply voltage and is able to increase the operating speed at a low operating voltage.

Dependencies are inferred from the claim text.