Threaded interpretive data processor

A signal processor for executing multiple tasks within a single cycle of an onboard clock, comprising:

• a main signal bus for transmittal of data and program instructions therein;
• program instruction means for placing program instructions and data on said signal bus;
• a last-in first-out parameter stack for storing data therein, said parameter stack having:
• a plurality of data registers disposed in a parallel configuration, and
• stack pointer means operably associated with said plurality of data registers for determining the top priority of a selected one of said data registers with respect to the remaining ones of said plurality of data registers for data processing operations,
• the output and input of all of said data registers simultaneously addressable;
• a plurality of output parameter buses;
• first interfacing means for selectively connecting each of said output parameter buses to the output of a select one of said data registers;
• a plurality of input parameter buses;
• a second interfacing means for selectively connecting each of said input parameter buses to the input of a select one of said data registers;
• arithmetic logic means selectively interconnecting with said output parameter buses for performing arithmetic and logic operations upon the data as provided by outputs of select ones of said data registers;
• third interfacing means for selectively connecting the output of said arithmetic logic means with one of said input parameter buses such that the data output thereof is storable in a select one of said data registers;
• fourth interfacing means for selectively connecting one of said output parameter buses with one of said input parameter buses such that data in one of said data registers can be directly input to another of said data registers;
• control means for controlling said first, second, third, and fourth interfacing means and said arithmetic logic means to execute a given task on the data in said data registers;
• microcode storage means for storing a microcode instructions for said control means;
• and
• retrieving means operably connected to said signal bus and retrieving program instructions therefrom, said program instruction means controlling said microcode storage means in response to program instructions on said signal bus to output a selected microcode instruction to said control means such that the data stored in said data registers can be manipulated by said first, second, third, and fourth interfacing means and said arithmetic logic means by transferring data between respective data registers, by enabling arithmetic and logic operations to be performed upon the data provided by the outputs of select ones of said data registers, by transferring data from said arithmetic logic means to inputs of select ones of said data registers, and by transferring data between respective data registers and said signal bus as determined by said selected microcode instruction.

A threaded interpretive data processor, comprising:

• a signal bus for transmittal of data and program instructions therein;
• program means for placing program instructions on said signal bus;
• a last-in first-out data stack having a plurality of data registers for storage of data therein, each of said data registers simultaneously addressable to input data into a plurality of said data registers and to output data from a plurality of said data registers;
• arithmetic logic means having at least two inputs for performing arithmetic and logic operations on data input thereto;
• first bus means operably connecting the outputs of said plurality of data registers with one input of said arithmetic logic means for transferring data from a select one of said data registers to said one input of said arithmetic logic means;
• second bus means operably connecting the outputs of said plurality of data registers with another input of said arithmetic logic means for transferring data from a select one of said data registers to said another input of said arithmetic logic means;
• third bus means operably connecting the output of said arithmetic logic means with the inputs of said plurality of data registers and said signal bus for selectively transferring the output of said arithmetic logic means to a select one of said data registers or to said signal bus;
• fourth bus means operably connecting said second bus means with the inputs of said plurality of data registers for transferring data from the second bus means to the input of a select one of said data registers;
• microcode storage means for storing microcode instructions at predetermined address locations therein, said microcode instructions stored in said microcode storage means being operable for controlling said first, second, third and fourth bus means and said arithmetic logic means;
• addressing means operably connected to said signal bus for accessing program instructions from said program means and addressing said microcode storage means in response to said program instructions to output select ones of the stored microcode instructions;
• and
• control means for controlling data flow on said first, second, third and fourth bus means and arithmetic logic means in response to microcode instructions selected by said addressing means such that data stored in said data registers in said data stack can be simultaneously manipulated and operated thereon by said arithmetic logic means by transferring data between respective data registers, by enabling arithmetic and logic operations to be performed upon the data provided by outputs of select ones of said data registers, by transferring data from said arithmetic logic means to inputs of select ones of said data registers, and by transferring data between respective data registers and said signal bus as determined by said selected microcode instructions.

A threaded interpretive data processor, comprising:

• a signal bus for transmittal of data and program instructions therein;
• a primary last-in first-out data stack having a plurality of primary data registers for storage of data therein, said primary data registers simultaneously addressable for input of data thereto or retrieval of data therefrom;
• an arithmetic logic unit for performing arithmetic and logic operations on data input thereto, said arithmetic logic unit having two inputs and one output;
• first interface/select means operably connecting the outputs of said primary data registers with one input of said arithmetic logic unit for selecting data from one of said primary data registers for input to said one input of said arithmetic logic unit;
• second interface/select means operably connecting the outputs of said primary data registers with the other input of said arithmetic logic unit for selecting data from one of said primary data registers for input to said other input of said arithmetic logic unit;
• third interface/select means operably connecting the inputs of said primary data registers or said signal bus with the output of said arithmetic logic unit for selecting either one of said primary data registers or said signal bus and transferring data from the output of said arithmetic logic unit to the selected one of said primary data registers on said signal bus;
• fourth interface/select means operably connecting the inputs of said primary data registers with said second interface/select means for selecting one of said primary data registers and transferring data from said second interface/select means to the input of the selected one of said primary data registers;
• control means for controlling the operation of said first, second, third and fourth interface/select means and said arithmetic logic unit in response to microcode instuctions such that data stored in said primary data registers can be manipulated by transferring data between respective primary data registers, by enabling arithmetic and logic operations to be performed upon the data provided by outputs of select ones of said primary data registers, by transferring data from said arithmetic logic unit to inputs of select ones of said primary data registers, and by transferring data between respective primary data registers and said signal bus;
• a read only memory for storing the microcode instructions at predetermined address locations therein;
• first address means for addressing said predetermined address location in said read only memory to retrieve select ones of the microcode instructions, said first address means being operably connected to said signal bus;
• storage means for storing microcode addresses for said read only memory, said storage means being operably connected to said signal bus;
• programming means for placing program signals on said signal bus;
• and
• second address means for addressing said storage means in response to program signals placed on said signal bus from said programming means, a sequence of microcode addresses being accessed from said storage means and placed on said signal bus in response to the addressing of said storage means by said second address means for retrieval by said first address means to address one of said predetermined address locations in said read only memory for retrieving a selected one of said microcode instructions to provide instructions for said control means to control said first, second, third and fourth interface/select means and said arithmetic logic unit to manipulate data stored in said primary data registers.

A threaded interpretive data processor, comprising:

• an address bus;
• a last-in first-out data stack having a plurality of data registers for storage of data therein, each of said data registers simultaneously addressable to input data into a plurality of said data registers and to output data from a plurality of said data registers;
• arithmetic logic means having an output and at least two inputs for performing arithmetic and logic operations on data input thereto;
• first bus means operably connecting the outputs of said plurality of data registers with one input of said arithmetic logic means for transferring data from a select one of said data registers to said one input of said arithmetic logic means;
• second bus means operably connecting the outputs of said plurality of data registers with another input of said arithmetic logic means for transferring data from a select one of said data registers to said another input of said arithmetic logic means;
• third bus means operably connecting the output of said arithmetic logic means with the inputs of said plurality of data registers and said main signal bus for selectively transferring the output of said arithmetic logic means to a select one of said data registers or to said main signal bus;
• fourth bus means operably connecting said second bus means with the inputs of said plurality of data registers for transferring data from the second bus means to the input of a select one of said data registers;
• microcode storage means operably connected to said main signal bus and said address bus, said microcode storage means defining a first level memory for storing microcode instructions in the form of addresses at predetermined address locations therein, said microcode instructions stored in said microcode storage means being operable for controlling said first, second, third and fourth bus means and said arithmetic logic means;
• addressing means operably connected to said main signal bus for addressing said microcode storage means in response to program instructions to output select ones of the stored microcode instructions from said microcode storage means, said addressing means including an instruction register connected to said main signal bus for receiving a coded address as program instructions from said main signal bus, and an address decoder interposed between said instruction register and said microcode storage means and operable to receive a coded address output from said instruction register for input to said microcode storage means as a decoded address;
• a control latch disposed at the output of said microcode storage means for receiving the addressed microcode instruction as output from said microcode storage means in a latched condition therein;
• control means for controlling data flow on said first, second, third and fourth bus means and arithmetic logic means in response to microcode instructions selected from said microcode storage means as provided thereto by said instruction register and said address decoder such that data stored in said data registers in said data stack can be simultaneously manipulated and operated thereon by said arithmetic logic means by transferring data between respective data registers, by enabling arithmetic and logic operations to be performed upon the data provided by outputs of select ones of said data registers, by transferring data from said arithmetic logic means to inputs of select ones of said data registers, and by transferring data between respective data registers and said main signal bus as determined by said selected microcode instructions;
• microcode address storage means operably connected to said main signal bus and to said address bus, said microcode address storage means defining a second level memory for storing a plurality of lists of microcode addresses at select locations therein, each said list containing a sequence of microcode addresses;
• means for addressing said microcode address storage means to access a selected list of microcode addresses in response to program instructions placed on said main signal bus for placing said microcode addresses of the accessed selected list on said main signal bus in sequence, said means for addressing said microcode address storage means including an instruction pointer connected to said main signal bus and to said address bus and interposed therebetween, said instruction pointer comprising a data register for clocking through an address from the main signal bus to said address bus for input to said microcode address storage means;
• said microcode addresses of the accessed selected list from said microcode address storage means being placed on said main signal bus in dependence upon the output of a predetermined functional microcode instruction by said control latch as output from said microcode storage means;
• and
• said control means being operably associated with said list-selecting addressing means to sequentially provide said microcode addresses in the selected one of said lists to said microcode storage means to output select ones of the stored microcode instructions corresponding to the microcode addresses included in the selected list such that the microcode instruction location at each microcode address location of said microcode storage means causes said control means to manipulate the data in said data stack.