Apparatus for allowing external control of local bus read using zero wait stats input of combined I/O and DRAM controller

A semiconductor chip for providing support circuitry to facilitate the implementation of a computer system with a microprocessor, comprising:

• an I/O bus controller, having inputs for coupling to a local bus coupled to said microprocessor and outputs for coupling to a system bus not directly connected to said microprocessor, for providing I/O cycle timing signals to said outputs unless an inhibit signal is received on an inhibit input, and including a zero wait state input for receiving an external zero wait state signal indicating that said I/O cycle timing signals can be completed earlier;
• a DRAM controller, having inputs and outputs for coupling to said local bus, for providing memory cycle timing signals to said local bus;
• a zero wait state/local bus access input pin, coupled to said zero wait state input of said I/O bus controller, for providing a zero wait state/local bus access signal indicating the presence of either said external zero wait state signal or a local bus access signal from an external device doing an operation on said local bus;
• a memory/input-output pin for providing a memory/input-output signal from said microprocessor indicating a memory cycle in a first state and an I/O cycle in a second state;
• an OR logic gate for inhibiting the provision of said I/O cycle timing signals by said I/O bus controller in response to the presence of said zero wait state/local bus access signal or the control of a cycle by said DRAM controller, said OR logic gate having a first input coupled to said zero wait state/local bus access input pin, a second input coupled to an output of said DRAM controller, and an output coupled to an inhibit input of said I/O bus controller;
• an AND gate having an output coupled to an inhibit input of said DRAM controller, a first input coupled to said memory/input-output pin, and a second input coupled to said zero wait state/local bus access pin;
• an open collector line coupled to said zero wait state/local bus access input pin;
• and
• a pull-up resistor coupled to said open collector line.