Emulation device for driving a LCD with signals formatted for a CRT display
AssigneeSeiko Epson Corporation
InventorKazuaki Inoue
Life of this patent
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Abstract
An interface device for changing the serial data format of the video signal output of a computer intended for display on a cathode ray tube, to a video signal having parallel data format for a liquid crystal display is provided. The device includes a read/write control circuit which responds to a clock signal corresponding to the synchronizing signal of the serial signal and to an asynchronous clock signal. Data signals which were removed from the serial signal and temporarily stored in memory are read out as parallel data signals at the next read cycle when read address counter is counted.
Claims13
An interface device for reformatting data containing input video signal, the interface device comprising:
- input means for receiving the input video signals, the input video signals containing data signals in an input;
- memory means for temporary storage of data signals received from the input means, the memory means having addresses at which the data signals are stored;
- first clock means for providing a first clock signal, the clock means being responsive to the input video signal;
- write counter means responsive to the first clock signal for providing at least one write address signal to the memory means;
- second clock means for providing a second clock signal which is asynchronous with the input video signal and the first clock signal;
- read counter means responsive to the second clock signal for providing at least one read address signal to the memory from which data signals are read, and
- read/write control means responsive to the first and second clock signals as inputs, the control means dividing a memory cycle synchronized with the one of the first clock signal and the second clock signal having the shorter cycle so as to produce one writing cycle and one reading cycle in one memory cycle, and controlling the effectuation of the writing operation and the reading operation so that the one of the writing operation and the reading operation which has the shorter corresponding clock signal is always effected in one of the divided memory cycle and the other operation is effected in the other cycle immediately after the counting of the counter means responsive to the clock signal with the longer cycle.
Dependencies are inferred from the claim text.