N-byte stack-oriented CPU using a byte-selecting control for enhancing a dual-operation with an M-byte instruction word user program where M<N<2M

An apparatus for enhancing the operation of an M-Byte instruction word CPU operating user programs on an N-Byte instruction word CPU where N is greater than M and less than 2M, comprising:

• an N-Byte instruction word CPU having an N-Byte instruction register;
• a main memory for supply either N-Byte or M-Byte instruction words to said N-Byte instruction register;
• a selection means for selecting an M-Byte instruction word mode of operation;
• an operation code MUX connected to all bytes of said N-Byte instruction register for loading only M-Byte instruction words selected by said selection means and for providing one byte operational code output to an operational code register;
• a parameter code MUX connected to all bytes of said N-Byte instruction register for loading only remaining bytes of said M-Byte instruction words selected by said selection means and for providing a parameter code output to a register file;
• and,
• wherein said selection means coupled to said operational code MUX and parameter code MUX for controlling bytes selection of said operational code MUX and parameter MUX in order to converting said N-Byte instruction word CPU to an M-Byte instruction word CPU.