US 5,179,686 AGranted

Method for automatically detecting the size of a memory by performing a memory warp operation

AssigneeNCR Corporation

InventorDaniel F. White

Life of this patent

Estimating the term…

Abstract

A method for detecting the size of a DRAM memory includes the steps of establishing a table of memory bank configurations each having a different memory capacity, selecting one of the memory configuration, writing and reading a data word at the lowest address in the bank having the highest memory capacity, writing a data word at an address higher than the lowest address, reading the data word at the lowest address and storing the selected memory configuration in a storage register as the memory configuration of the memory when the data word read at the lowest address was not the word written at the highest address.

Claims5

Dependent claims

In an apparatus which includes a central processing unit and a memory unit having banks of variable memory capacities, a method for automatically detecting the size of the memory unit upon power being applied to the apparatus comprising the steps of:

storing data representing a plurality of memory units each with different storage capacities in a first storage unit;
selecting from the first storage unit a first and second memory unit as the size of the memory unit;
writing a first binary word at the lowest address in the memory unit having the largest storage capacity;
performing a first read operation at said lowest address;
writing a second binary word at an address that is higher than said lowest address in response to reading the first binary word at said lowest address in the memory unit;
performing a second read operation at said lowest address in the memory unit;
selecting from the first storage unit as the size of the memory unit a third memory unit having a first memory capacity when the second binary word is read by the second read operation;
writing a third binary word at an address which is higher than the lowest address i the third memory unit;
performing a third read operation at the lowest address in the third memory unit;
selecting from the first storage unit as the size of the memory unit the third memory unit having a second memory capacity which is less than the first memory capacity and a fourth memory unit having a third memory capacity when the third binary word is read by said third read operation;
writing a fourth binary word at the lowest address in the third memory unit;
performing a fourth read operation at the lowest address in the third memory unit;
storing in a second storage unit the data representing the first and second memory units as representing the memory capacity of the memory unit when the second binary word is not read by the second read operation;
and
storing data in the second storage unit representing the third memory unit having the second memory capacity as the storage capacity of the memory unit when the fourth binary word is not read by the fourth read operation.

12 more elements

Dependencies are inferred from the claim text.

patentgrep

Loading patent…

Abstract

storing data representing a plurality of memory units each with different storage capacities in a first storage unit;
selecting from the first storage unit a first and second memory unit as the size of the memory unit;
writing a first binary word at the lowest address in the memory unit having the largest storage capacity;
performing a first read operation at said lowest address;
writing a second binary word at an address that is higher than said lowest address in response to reading the first binary word at said lowest address in the memory unit;
performing a second read operation at said lowest address in the memory unit;
selecting from the first storage unit as the size of the memory unit a third memory unit having a first memory capacity when the second binary word is read by the second read operation;
writing a third binary word at an address which is higher than the lowest address i the third memory unit;
performing a third read operation at the lowest address in the third memory unit;
selecting from the first storage unit as the size of the memory unit the third memory unit having a second memory capacity which is less than the first memory capacity and a fourth memory unit having a third memory capacity when the third binary word is read by said third read operation;
writing a fourth binary word at the lowest address in the third memory unit;
performing a fourth read operation at the lowest address in the third memory unit;
storing in a second storage unit the data representing the first and second memory units as representing the memory capacity of the memory unit when the second binary word is not read by the second read operation;
and
storing data in the second storage unit representing the third memory unit having the second memory capacity as the storage capacity of the memory unit when the fourth binary word is not read by the fourth read operation.

12 more elements