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AssigneeSun Microsystems, Inc.
InventorEric H. Jensen
Estimating the term…
A processor which has a plurality of windowed registers. Each of the windowed registers comprise IN, OUT and LOCAL window registers. The IN registers of each window are addressable as the OUT registers of a logically-adjacent succeeding window. The processor also has a cache of at least four sets of cache registers with switchable addresses. Each set of cache registers is capable of holding data of the IN, OUT or LOCAL window registers. The addresses of each set of cache registers are changed to the addresses of a different set of cache registers when the current window changes during a save or restore operation.
A processor that executes a plurality of procedures wherein at least one of the procedures calls another of the procedures, said processor coupled to a plurality of windowing apparatae, each windowing apparatus of the windowing apparatae having a current window corresponding to an executing procedure, a previous window corresponding to a procedure which called the executing procedure and a next window corresponding to a procedure which is called by the executing procedure, each window having at least one IN register, each of the IN registers containing an input parameter value passed to the corresponding procedure by a calling procedure, at least one OUT register, each of the OUT registers containing an output parameter value passed from the corresponding procedure to a called procedure and at least one LOCAL register, wherein the IN register of a particular window is the OUT register of a logically succeeding window, the processor comprising:
A processor that executes a plurality of procedures wherein at least one of the procedures calls another of the procedures, said processor coupled to a plurality of windowing apparatae, each windowing apparatus of the windowing apparatae having a current window corresponding to an executing procedure, a previous window corresponding to a procedure which called the executing procedure and a next window corresponding to a procedure which is called by the executing procedure, each window having at least one IN register, each of the IN registers containing an input parameter value passed to the corresponding procedure by a calling procedure, at least one OUT register, each of the OUT registers containing an output parameter passed from the corresponding procedure to a called procedure and at least one LOCAL register, wherein the IN register of a particular window is the OUT register of a logically succeeding window, the processor comprising:
In a processor comprising an arithmetic and logic unit (ALU), said processor executing a plurality of procedures wherein at least one of the procedures calls another of the procedures, the processor coupled to a plurality of windowing apparate, each windowing apparatus to the windowing apparatae having a current window corresponding to an executing procedure, a previous window corresponding to a procedure which called the executing procedure, and a next window corresponding to a procedure which is called by the executing procedure, each window having at least one IN register, each of the IN registers containing an input parameter passed to the corresponding procedure by a calling procedure, at least one OUT register, each of the OUT registers containing an output parameter passed from the corresponding procedure to a called procedure and at least one LOCAL register, wherein the IN register of a particular window is the OUT register of a logically succeeding window, the processor further comprising a windowed register cache, coupled between the windowing apparatae and the ALU, said cache comprising at least four cache registers, each of the cache registers accessible by the ALU as a cache IN register, a cache LOCAL register or a cache OUT register, the cache registers having a logical sequence whereby the last cache register is logically adjacent to the first cache register such that if a cache register of the at least four registers is designated as register L, register L+1 is the cache register logically succeeding the register L, register L+2 is the cache register logically succeeding the register L+1, register L+3 is the cache register logically succeeding the register L+2, register L-1 is the cache register logically preceding the register L, register L-2 is the cache register logically preceding the register L-1, register L-3 is the cache register logically preceding the register L-2, a method for caching the windows to increase the speed of access to the windows, said method comprising the steps of:
Dependencies are inferred from the claim text.
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No related US applications are recorded in the indexed filing history.
Saving or restoring of program or task context: with multiple register sets
According to context, e.g. thread buffers: register windows
Organisation of register space, e.g. banked or distributed register file: extension of register space, e.g. register cache
Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches: with…
Term ended 15 May 2010 (estimated)
USPTO file history isn’t available for this patent, so only indexed dates are shown.
1. Field of the Invention:
This invention relates to computer systems and, more particularly, to methods and apparatus for implementing processors used in reduced instruction set computers.
2. History of the Prior Art:
FIG. 1 is a block diagram illustrating three logically-adjacent sets of register windows in the SPARC architecture.
FIG. 2 is a diagram illustrating an array of register windows in the SPARC architecture.
FIG. 3 is a block diagram illustrating an improved current window cache constructed in accordance with the invention.
Some portions of the detailed descriptions which follow are presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art.
An algorithm is here, and generally, conceived to be a self-consistent sequence of steps leading to a desired result. The steps are those requiring physical manipulations of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like. It should be borne in mind, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities.
Further, the manipulations performed are often referred to in terms, such as adding or comparing, which are commonly associated with mental operations performed by a human operator. No such capability of a human operator is necessary or desirable in most cases in any of the operations described herein which form part of the present invention; the operations are machine operations. Useful machines for performing the operations of the present invention include general purpose digital computers or other similar devices. In all cases the distinction between the method operations in operating a computer and the method of computation itself should be borne in mind. The present invention relates to apparatus and to method steps for operating a computer in processing electrical or other (e.g. mechanical, chemical) physical signals to generate other desired physical signals.