Method and apparatus for current window cache with switchable address and out cache registers

A processor that executes a plurality of procedures wherein at least one of the procedures calls another of the procedures, said processor coupled to a plurality of windowing apparatae comprising a plurality of window registers, each windowing apparatus of said windowing apparatae having a current window corresponding to an executing procedure, a previous window corresponding to a procedure which called the executing procedure and a next window corresponding to a procedure which is called by the executing procedure, each window having at least one IN register containing at least one parameter passed to the corresponding procedure by a calling procedure, at least one OUT register containing at least one parameter passed from the corresponding procedure to a called procedure and at least one LOCAL register, wherein the IN register of a particular window is the OUT register of a logically succeeding window, the processor comprising:

• an arithmetic and logic unit (ALU);
• a windowed register cache, coupled between the windowing apparatae and the ALU, said cache comprising a first register, a second register and a third register, each of the first, second and third registers having at least one identifying address, the first and third registers having a first and second address such that the first register is addressed using the first address when the third register is addressed using the second address and the third register is addressed using the first address when the first register is addressed using the second address, the contents of the current window contained in the cache such that the first register contains contents of the current window IN register and is addressed using the first address, the second register contains contents of the current window LOCAL register, the third register contains contents of the current window OUT register and is addressed using the second address, the first, second and third registers accessed by the ALU as containing the contents of the respective current window IN, LOCAL and OUT registers;
• said windowed register cache further comprising logic means for controlling loading of, and access to, said windowed register cache such that if the procedure corresponding to the current window calls the procedure corresponding to the next window, the first register is loaded with contents of the next window OUT register, the second register is loaded with contents of the next window LOCAL register, the address of the first register is changed to the second address and the address of the third register is changed to the first address, and the third, second and first registers are accessed by the ALU as containing the contents of the respective next window IN, LOCAL and OUT registers;
• if the procedure corresponding to the current window returns to the procedure corresponding to the previous window, the third register is loaded with the contents of the previous window IN register, the second register is loaded with the contents of the previous window LOCAL register, the address of the first register is changed to the second address and the address of the third register is changed to the first address, and the first, second and third registers are accessed by the ALU as containing the contents of the respective previous window IN, LOCAL and OUT registers;
• whereby the windowed registers are cached for quick access by the ALU and the amount of data transferred from the windowed registers to the cache is minimized for rapid update of the cache.

In a processor comprising an arithmetic and logic unit (ALU) said processor executing a plurality of procedures wherein at least one of the procedures calls another of the procedures, the processor coupled to a plurality of windowing apparatae, each windowing apparatus of said windowing apparatae having a current window corresponding to an executing procedure, a previous window corresponding to a procedure which called the executing procedure, and a next window corresponding to a procedure which is called by the executing procedure, each window having at least one IN register containing at least one parameter passed to the corresponding procedure by a calling procedure, at least one OUT register containing at least one parameter passed from the corresponding procedure to a called procedure and at least one LOCAL register, wherein the IN register of a particular window is the OUT register of a logically succeeding window, a method for caching the windows to increase the speed of access to the windows, said method comprising the steps of:

• providing a windowed register cache, coupled between the windows and the ALU, the cache comprising a first register, a second register and a third register;
• loading contents of the current window into the cache such that the first register contains contents of the current window IN register, the second register contains contents of the current window LOCAL register and the third register contains contents of the current window OUT register;
• if the procedure corresponding to the current window calls the procedure corresponding to the next window, loading the first register with contents of the next window OUT register, the second register with contents of the next window LOCAL register;
• if the procedure corresponding to the current window returns to the procedure corresponding to the previous window, loading the third register with the contents of the previous window IN register, loading the second register with the contents of the previous window LOCAL register;
• whereby the ALU accesses the windowed register cache for quick access and the windowed register cache is rapidly updated by loading the minimum amount of data from the windowed registers.