Address/control signal input circuit for a cache controller which clamps the address/control signals to predetermined logic level clamp signal is received

A cache controller coupled to a cache memory for controlling the cache memory in response to a signal from a microprocessor, the cache controller comprising:

• an address signal input terminal and a control signal input terminal coupling through a bus to the microprocessor to receive an address signal and a control signal from the microprocessor;
• a clamp signal input terminal coupled to receive from the microprocessor a clamp signal which is rendered active when the microprocessor brings, into a high impedance condition, terminals of the microprocessor for outputting the address signal and the control signal, the bus being subjected to take an intermediate level between one logic level and another logic level by the microprocessor bringing the terminals of the microprocessor into the high impedance condition;
• a signal input circuit, coupled to the address signal input terminal and to the control signal input terminal, to receive signals on the bus to produce an internal address signal and an internal control signal;
• and
• means, coupled to the clamp signal input terminal and to the signal input circuit, for causing the signal input circuit to respond to the address signal and the control signal from the microprocessor to produce the internal address signal and the internal control signal, when the clamp signal is inactive, and for causing the signal input circuit to clamp the internal address signal and the internal control signal at a predetermined logic level irrespective of the intermediate level of the bus, when the clamp signal is active.

A cache controller coupled to a cache memory for controlling the cache memory in reponse to a signal from a microprocessor, the cache controller comprising:

• an address signal input terminal coupled to receive an address signal from the microprocessor;
• a clamp signal input terminal coupled to the microprocessor to receive a clamp signal which is rendered active when the microprocessor brings, into a high impedance condition, a terminal of the microprocessor for outputting the address signal;
• an address input circuit, coupled to the address signal input terminal, to produce an internal address signal;
• and
• means, coupled to the clamp signal input terminal and to the address input circuit, for causing the address input circuit to respond to the address signal from the microprocessor to produce the internal address signal, which changes between logic levels in response to a change in a logic level of the address signal, when the clamp signal is inactive, and for causing the address input circuit to clamp the internal address signal at a predetermined logic level irrespective of a potential level at the address signal input terminal, when the clamp signal is active.