Address selection circuit including address counters for performing address selection

An address selection circuit comprising:

• detecting means for receiving control bit data of a control bit part of an n-bit address selecting instruction which is read from a program ROM and which includes the control bit part having a group of j bits and a group of k bits and an operand part having m bits (n=j+k+m) the control bit data being represented by the j bits in the control bit part, the k bits in the control group part generally being available for other control use and normally being unused in the address selection mode, said detecting means outputting a first control signal when it detects from the j-bit control data that the instruction is one for address selection, and said detecting means outputting a second control signal when it detects from the j-bit control data that a number of bits of an address to be selected by the instruction is greater than or equal to m+1;
• said instruction operand part containing m bits of said address if said address has m+1 or more bits and said instruction control part containing in the k bit group those excess bits that exceed m in said address;
• m-bit address counter means, coupled to receive data of the operand part of said instruction and to provide outputs of said m-bit address counter means to said program ROM, for carrying out address selection and for outputting a first portion of the address corresponding to the address bits of the operand part of said instruction, when said detecting means detects the instruction for address selection, said m-bit address counter means being controlled in response to the first control signal output from said detecting means;
• first data entry gate means, responsive to the first control signal from said detecting means, for supplying said address bits of the operand part of said instruction to said m-bit address counter means when said detecting means detects said instruction to be one for address selection;
• k-bit (k.ltoreq.m) address counter means, coupled to receive said address bits in excess of m of the control bit part of said instruction and to provide outputs of said k-bit address counter means to said program ROM, for carrying out address selection and for outputting a second remaining portion of said address corresponding to the excess address bits of the control bit part of said instruction when said detecting means detects said instruction to be one for address selection and that the number of bits of the address to be selected is greater than or equal to m+1, said k-bit address counter means being controlled in response to the second control signal output from said detecting means, wherein the outputs of said m-bit address counter means and said k-bit address counter means are applied to said program ROM simultaneously;
• and
• second data entry gate means, responsive to the second control signal from said detecting means, for supplying said address bits in excess of m of the control bit part of said instruction to said k-bit address counter means when said detecting means detects said instruction to be one for address selection and that the number of bits of the address to be selected is greater than or equal to m+1.