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US 5,179,674 AGranted
Method and apparatus for predicting valid performance of virtual-address to physical-address translations
AssigneeDigital Equipment Corporation
InventorsDouglas D. Williams, David M. Fenwick, Timothy J. Stanley
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Abstract
A prediction logic device operating in conjunction with a vector processor to predict, before the completion of the translation of the virtual addresses of all of the data elements of a vector, the valid performance of all virtual-address to physical-address translations for the data elements of the vector. The prediction logic device asserts an MMOK signal to a scalar processor when it becomes known that no memory management fault and/or translation buffer miss will occur such that the scalar processor can resume vector instruction issue to the vector processor at the earliest possible time.
Claims6
A prediction logic device, which comprises:
- a computation device for receiving information relating to vector length and vector stride of a particular vector and serially receiving at least a portion of each of a set of virtual addresses corresponding to an ordered set of data elements of the particular vector;
- the computation device operating to calculate virtual address information relating to the last data element of the ordered set of data elements and based upon the information relating to vector length, vector stride and at least one of the virtual addresses of the set of virtual addresses, wherein said computation device includes a device for determining an upper bound approximation of the virtual address information relating to the last data element;
- a comparator coupled to the computation device, the comparator arranged to receive serially at least a portion of each of the set of virtual addresses, and operating to compare each of the at least a portion of each of the virtual addresses of the set of virtual addresses, serially, to the upper bound approximation of the virtual address information relating to the last data element;
- a translation buffer and access checking device arranged to receive serially translation buffer hit and miss information corresponding to the ordered set of data elements of the particular vector;
- and
- an MMOK signal output device coupled to the comparator and to the translation buffer and access checking device, the MMOK signal output device operating to assert an MMOK signal when:
- (i) the comparator indicates a first match between at least a portion of any one of the virtual addresses of the set of virtual addresses and the upper bound approximation of the virtual address information relating to the last data element;
- and
- (ii) the translation buffer hit and miss information indicates a valid translation buffer hit for the any one of the virtual addresses of the set of virtual addresses.
6 more elements
A prediction logic device which comprises:
- a computation device for receiving information relating to vector length and vector stride of the particular vector and serially receiving at least a portion of each of a set of virtual addresses corresponding to an ordered set of data elements of the particular vector;
- the computation device operating to calculate virtual address information relating to a last data element of the ordered set of data elements and based upon the information relating to vector length, vector stride and at least one of the virtual addresses of the set of virtual addresses;
- the computation device including a first device for continuously determining a remaining data element count, serially, for each one of the ordered set of data elements, a second device for determining the upper bound log base 2 of the remaining element count for each one of the ordered set of data elements and a third device for shifting left the vector stride by the upper bound log base 2 of the remaining element count for each one of the ordered set of data elements;
- the computation device further including an adder for adding, in sequence, each one virtual address of the set of virtual addresses to the vector stride shifted left by the third device by the log base 2 of the remaining element count for a one data element of the ordered set of data elements, which one data element corresponds to the one virtual address, to continuously calculate virtual address information relating to the last data element of the ordered set of data elements, serially, for each one of the ordered set of data elements;
- a comparator coupled to the computation device, the comparator arranged to receive serially at least a portion of each of the set of virtual address and operating to compare each one of the at least a portion of each one virtual address of the set of virtual addresses, serially, to the virtual address information relating to the last data element for the one data element corresponding to the one virtual address;
- a translation buffer and access checking device arranged to receive serially at least a portion of each of the set of virtual addresses corresponding to the ordered set of data elements of the particular vector and to generate translation buffer hit and miss information corresponding to the ordered set of data elements of the particular vector;
- and
- an MMOK signal output device coupled to the comparator and to the translation buffer and access checking device, the MMOK signal output device operating to assert an MMOK signal when:
- (i) the comparator indicates a first match between at least a portion of any one virtual address of the set of virtual addresses and the virtual address information relating to the last data element for the one data element corresponding to the any one virtual address;
- and
- (ii) the translation buffer hit and miss information indicates a valid translation buffer hit for the any one virtual address of the set of virtual addresses.
8 more elements
Dependencies are inferred from the claim text.