Apparatus and method for modeling parallel processing of instructions using sequential execution hardware

A method for modeling parallel processing of instructions using sequential execution hardware comprising:

• providing first, second and third combinational logic circuits, implementing a prefetch function, decode function and execution function, said combinational logic circuits receiving on first inputs thereof parallel processing execution instructions;
• providing first, second and third public status register outputs from a public status register for transferring data to second inputs of said combinational logic circuits;
• providing first, second and third working status register inputs from a working status register for receiving the data results produced by said combinational logic circuits;
• and,
• providing means for dividing a clock cycle into first and second clock portions, said first portion transferring data from said public status register output to said combinational logic and writing results from said combinational logic circuits to said working status register inputs, and during a second portion of said clock cycle, transferring data from said working status register to said public status registers, whereby instructions may be prefetched, decoded and executed sequentially over a time interval defined by a single clock cycle.

An apparatus for modeling parallel processing of instructions in a sequential execution system comprising:

• a trace register for providing a series of multidigit codes representing data which is produced during parallel processing;
• a combinational logic circuit for receiving each bit of said multidigit code, said logic circuit having a plurality of logic outputs for sequentially performing logical functions on said multidigit codes;
• a working status register having a plurality of inputs connected to said combinational logic circuit outputs;
• a public status register having a plurality of input lines connected to said working status register outputs and a plurality of outputs connected to a like number of inputs of said combinational logic circuit;
• and,
• a clock circuit for identifying the beginning of an interval in which subcircuits of said combinational logic circuit sequentially calculate a new set of logic output signals, and identifying the end of said interval, said clock circuit initiating transfer of the contents of said public status register to said combinational logic, and transferring the contents of said working status register to said public status register at the end of said interval, whereby transitional data produced by said combinational logic circuit during said interval does not reach said public status register.

A system for modeling computer instruction execution comprising:

• a public status register for holding data representative of the status of a computer processing system;
• a trace register for storing multidigit binary data representing processing data produced by a computer processing program;
• a combinational logic unit for receiving multibit data words from said public status register and said trace register, said combinational logic unit producing output data over a sequential computational interval;
• a working status register connected to said combinational logic unit for receiving output data sequentially produced by said combinational logic unit, and transferring data in response to a clock signal to said public status register;
• and,
• a clock signal generator for generating first and second clock signals for defining said computational interval, said first clock signal being applied to said public status register to transfer its contents to the combinational logic, and said second clock signal representing the end of said computation interval, enabling said working status register to transfer the data to said public status register when said computational interval is completed.