US 5,179,671 AGranted

Apparatus for generating first and second selection signals for aligning words of an operand and bytes within these words respectively

AssigneeBull HN Information Systems Inc.

InventorsRichard P. Kelly, Robert V. Ledoux

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Abstract

A data processing system includes cache memories for storing instructions and operands. An execution unit stores instructions in an instruction FIFO, operands in a data FIFO and offsets in an offset FIFO. Offsets indicate the location of operands relative to a memory word boundary. Instructions read from the instruction FIFO are applied to a control store subsystem which reads out a firmware word. Specified firmware bits condition multiplexers in the data path to align the operands on the fly during the execution of the instruction.

Claims19

Dependent claims

A data processing system for aligning operands during an execution of instructions comprising:

memory means including instruction memory means for storing a plurality of instructions and data memory means for storing a plurality of operands in word locations, said word locations having a word boundary starting with an even address location;
instruction register means coupled to said instruction memory means for storing said plurality of instructions received from said instruction memory means, one of said plurality of instructions specifying an operand type, and a word location of an operand;
data register means coupled to said data memory means for storing said plurality of operands received from said data memory means;
offset register means coupled to said instruction memory means for storing and generating a plurality of offset signals indicating said word location of said operand relative to said word boundary;
control store means coupled to said instruction register means and responsive to said one of said plurality of instructions for generating a plurality of control signals;
decoder means coupled to said control store means and responsive to a first plurality of said control signals for generating a plurality of type signals indicating said operand type used in said execution of said one of said plurality of instructions;
first logic means coupled to said offset register means and said decoder means and responsive to said plurality of type signals and said plurality of offset signals for generating a first plurality of selection signals for aligning words of said operand and a second plurality of selection signals for aligning bytes within said words of said operand;
first multiplexer means coupled to said data register means and said first logic means and responsive to said first plurality of selection signals for aligning said during said execution of said one of said plurality of instructions;
second logic means coupled to said control store means sand said first multiplexer means and responsive to a second plurality of said control signals for performing logic functions on said aligned operand in accordance with said one of said plurality of instructions to generate a second operand;
second multiplexer means coupled to said first logic means and said second logic means sand responsive to said second plurality of selection signals for aligning said second operand;
said data memory means further coupled to said second multiplexer means for storing said aligned second operand at a location specified by said one of said plurality of instructions wherein said aligned second operand is a result of said execution of said one of said plurality of instructions on said operand.

8 more elements

A data processing system for aligning operands during an execution of instructions comprising:

memory means including instruction memory means for storing a plurality of instructions and data memory means for storing a plurality of operands in word locations, said word locations having a word boundary starting with an even address location;
instruction register means coupled to said instruction memory means for storing said plurality of instructions received from said instruction memory means, one of said plurality of instructions specifying an operand type, and a word location of an operand;
data register means coupled to said data memory means for storing said plurality of operands received from said data memory means;
offset register means coupled to said instruction memory means for storing and generating a plurality of offset signals indicating said word location of said operand relative to said word boundary;
control store means coupled to said instruction register means and responsive to said one of said plurality of instructions for generating a plurality of control signals;
decoder means coupled to said control store means and responsive to a first plurality of said control signals for generating a plurality of type signals indicating said operand type used in said execution of said one of said plurality of instructions;
first logic means coupled to said offset register means and said decoder means and responsive to said plurality of type signals and said plurality of offset signals for generating selection signals;
multiplexer means coupled to said data register means and said first logic means and responsive to said selection signals for aligning said operand during said execution of said one of said plurality of instructions;
second logic means coupled to said control store means and said multiplexer means and responsive to a second plurality of said control signals for performing logic functions on said aligned operand in accordance with said one of said plurality of instructions to generate a second operand;
register file means coupled to said control store means and said second logic means for storing said second operand in one of a plurality of registers specified said plurality of control signals wherein said aligned second operand is a result of said execution of said one of said plurality of instructions on said operand.

7 more elements

A data processing system for aligning operands during an execution of instructions comprising:

memory means for storing said instructions, said operands and offset signals, said offset signals specifying a location of said operands within a word boundary, one of said instructions specifying an operand type, and a word location of an operand;
control store means coupled to said memory means and responsive to said one of said instructions for generating a plurality of control signals;
first logic means coupled to said memory means and said control store means and responsive to a first plurality of said control store signals and said offset signals for generating a plurality of selection signals;
first multiplexer means coupled to said memory means sand said first logic means and responsive to a first plurality of said selection signals for aligning said operand;
second logic means coupled to said control store means and said first multiplexer means and responsive to a second plurality of said control signals for performing logic functions on said aligned operand in accordance with said one of said instructions to generate a second operand;
second multiplexer means coupled to said first and said second logic means and responsive to a second plurality of said selection signals for aligning said second operand;
said memory means further coupled to said second multiplexer means for storing said aligned second operand at a location specified by said one of said instructions wherein said aligned second operand is a result of said execution of said one of said instructions on said operand.

4 more elements

Dependencies are inferred from the claim text.

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Abstract

A data processing system for aligning operands during an execution of instructions comprising:

memory means including instruction memory means for storing a plurality of instructions and data memory means for storing a plurality of operands in word locations, said word locations having a word boundary starting with an even address location;
instruction register means coupled to said instruction memory means for storing said plurality of instructions received from said instruction memory means, one of said plurality of instructions specifying an operand type, and a word location of an operand;
data register means coupled to said data memory means for storing said plurality of operands received from said data memory means;
offset register means coupled to said instruction memory means for storing and generating a plurality of offset signals indicating said word location of said operand relative to said word boundary;
control store means coupled to said instruction register means and responsive to said one of said plurality of instructions for generating a plurality of control signals;
decoder means coupled to said control store means and responsive to a first plurality of said control signals for generating a plurality of type signals indicating said operand type used in said execution of said one of said plurality of instructions;
first logic means coupled to said offset register means and said decoder means and responsive to said plurality of type signals and said plurality of offset signals for generating a first plurality of selection signals for aligning words of said operand and a second plurality of selection signals for aligning bytes within said words of said operand;
first multiplexer means coupled to said data register means and said first logic means and responsive to said first plurality of selection signals for aligning said during said execution of said one of said plurality of instructions;
second logic means coupled to said control store means sand said first multiplexer means and responsive to a second plurality of said control signals for performing logic functions on said aligned operand in accordance with said one of said plurality of instructions to generate a second operand;
second multiplexer means coupled to said first logic means and said second logic means sand responsive to said second plurality of selection signals for aligning said second operand;
said data memory means further coupled to said second multiplexer means for storing said aligned second operand at a location specified by said one of said plurality of instructions wherein said aligned second operand is a result of said execution of said one of said plurality of instructions on said operand.

8 more elements