US 5,179,667 AGranted

Synchronized DRAM control apparatus using two different clock rates

AssigneeSilicon Graphics, Inc.

InventorSanjay Iyer

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Abstract

A control apparatus for a computer is described that includes an arbiter circuit for selecting a first controller for supplying the memory of the computer with a first plurality of addresses from a first bus at a first rate and for selecting the second controller for supplying the memory of the computer with a second plurality of addresses from a second bus at a second rate. The first and second controllers are selected such that the first and second controllers do not supply the memory with more than one memory address at a time. A method for controlling the use of a computer bus is also described. A plurality of requests to use the bus are received. A length of a first period for use of the bus and a length of a second period for use of the bus are preselected. Each of the plurality of requests are granted.

Claims7

Dependent claims

In a computer that includes a dynamic random access memory (DRAM), a first clock for supplying a first clock signal at a first clock rate, a second clock for supplying a second clock signal at a second clock rate different from the first clock rate, a first bus for transferring a first address at a rate synchronized with the first clock rate, and a second bus for transferring a second address at a rate synchronized with the second clock rate, a DRAM control apparatus comprising:

a first multiplexer coupled to the DRAM;
a second multiplexer coupled to the DRAM;
a first controller, coupled to the first bus and to the first and second multiplexers, clocked by the first clock, and synchronized with the first clock rate for controlling the DRAM, for supplying the DRAM via the first multiplexer with the first address from the first bus synchronized with the first clock rate, for supplying the DRAM via the second multiplexer with a first strobe signal synchronized with the first clock rate, and for synchronizing the DRAM, the first multiplexer, and the second multiplexer with the first clock rate;
a second controller, coupled to the second bus and to the first and second multiplexers, clocked by the second clock, and synchronized with the second clock rate for controlling the DRAM, for supplying the DRAM via the first multiplexer with the second address from the second bus synchronized with the second clock rate, for supplying the DRAM via the second multiplexer with a second strobe signal synchronized with the second clock rate, and for synchronizing the DRAM, the first multiplexer, and the second multiplexer with the second clock rate;
an arbiter coupled to the first and second controllers for selectively engaging the respective first controller and the second controller based on a predetermined priority and timing scheme, wherein the first and second controllers are not engaged simultaneously, wherein when the first controller is engaged, the first controller (1) controls the DRAM, (2) supplies the DRAM via the first multiplexer with the first address from the first bus synchronized with the first clock rate, (3) supplies the DRAM via the second multiplexer with the first strobe signal synchronized with the first clock rate, and (4) synchronizes the DRAM, the first multiplexer, and the second multiplexer with the first clock rate, wherein when the second controller is engaged, the second controller (1) controls the DRAM, (2) supplies the DRAM via the first multiplexer with the second address from the second bus synchronized with the second clock rate, (3) supplies the DRAM via the second multiplexer with the second strobe signal synchronized with the second clock rate, and (4) synchronizes the DRAM, the first multiplexer, and the second multiplexer with the second clock rate.

2 more elements

A digital computer comprising:

a central processing unit;
a dynamic random access memory (DRAM);
a first clock for supplying a first clock signal at a first rate;
a second clock for supplying a second clock signal at a second clock rate different from the first clock rate;
a first bus for transferring a first address at a rate synchronized with the first clock rate;
a second bus for transferring a second address at a rate synchronized with the second clock rate;
a first multiplexer coupled to the DRAM;
a second multiplexer coupled to the DRAM;
a first controller coupled to the first bus, to the first multiplexer, and to the second multiplexer, clocked by the first clock, and synchronized with the first clock rate for controlling the DRAM, for supplying the DRAM via the first multiplexer with the first address from the first bus synchronized with the first clock rate, for supplying the DRAM via the second multiplexer with a first strobe signal synchronized with the first clock rate, and for synchronizing the DRAM, the first multiplexer, and the second multiplexer with the first clock rate,
a second controller coupled to the second bus, to the first multiplexer, and to the second multiplexer, clocked by the second clock, and synchronized with the second clock rate for controlling the DRAM, for supplying the DRAM via the first multiplexer with the second address from the second bus synchronized with the second clock rate, for supplying the DRAM via the second multiplexer with a second strobe signal synchronized with the second clock rate, and for synchronizing the DRAM, the first multiplexer, and the second multiplexer with the second clock rate;
an arbiter coupled to the first and second controller for selectively engaging the respective first controller and the second controller based upon a predetermined priority and timing scheme, wherein the first and second controllers are not engaged simultaneously, wherein when the first controller is engaged, the first controller (1) controls the DRAM, (2) supplies the DRAM via the first multiplexer with the first address from the first bus synchronized with the first clock rate, (3) supplies the DRAM via the second multiplexer with the first strobe signal synchronized with the first clock rate, (4) synchronizes the DRAM, the first multiplexer, and the second multiplexer with the first clock rate, wherein when the second controller is engaged, the second controller (1) controls the DRAM, (2) supplies the DRAM via the first multiplexer with the second address from the second bus synchronized with the second clock rate, (3) supplies the DRAM via the second multiplexer with the second strobe signal synchronized with the second clock rate, and (4) synchronizes the DRAM, the first multiplexer, and the second multiplexer with the second clock rate.

8 more elements

Dependencies are inferred from the claim text.