Data transfer controller

An integrated data transfer controller for use with a host processor, the integrated data transfer controller having a plurality of data transfer channels and the controller also providing a bus request signal to the host processor to request acquisition of bus mastership from the host processor and acquiring the bus mastership upon receiving a bus acknowledge signal from the host processor, the integrated data transfer controller comprising:

• burst-number registers for respectively storing predetermined value defining the number of data transfers in the individual data transfer channels;
• and
• a transfer control means including,
• total-burst-number register means for storing a predetermined value defining the number of continuous data transfers extending over at least two of the plurality of data transfer channels,
• wherein the transfer control means provides the bus request signal to acquire the bus membership upon receiving a signal representative of data transfer enable status of one of the plurality of data transfer channels,
• wherein the transfer control means controls the number of the continuous data transfers in the individual data transfer channels on the basis of the values set in each of the burst-number registers, respectively, and
• wherein the transfer control means maintains the bus mastership for other data transfer channels which are in the data transfer enable status until the number of the continuous data transfers after the acquisition of the bus mastership, reaches the value set in of the total-burst-number register.

A communication control device for use with a host processor providing a bus acknowledge signal to the communication control device upon receiving a bus request signal from the communication control device, and a main memory, the communication control device comprising:

• a central processing unit for executing protocol processing;
• a data memory for storing control data for the central processing unit therein;
• a circuit control unit for receiving and transmitting serial data to and from the communication control device the circuit control unit receiving serial data from external devices;
• data buffer means coupled to the circuit control unit and for storing received data and data to be transmitted therein;
• and
• a direct memory access controller coupled to the data memory, to the data buffer means and to the main memory, the direct memory access controller having a first channel for transferring the data in the data buffer means to the main memory, a second channel for transferring data in the main memory to the data buffer means as the data to be transmitted and a third channel for transferring data between the data memory and the main memory, each of the first, second, and third channels having,
• a status register in which status data indicative of data transfer enable status of the individual channels is selectively set, wherein each of the first, second, and third channels provides a request signal when the status is set into the corresponding status register, and
• a burst-number register for respectively storing predetermined values defining the number of data transfer words in the individual channels,
• the direct memory access controller further including a transfer control unit having,
• total-burst-number register means for storing a predetermined value defining the number of continuous data transfers extending over at least two of the first, second, and third channels,
• wherein the transfer control unit provides the bus request signal to acquire the burst mastership upon receiving at least one request signal from one of the first to third channels,
• wherein the transfer control unit controls the number of the continuous data transfers in the individual channels on the basis of the values of set in each of the burst-number registers, respectively, and
• wherein the transfer control unit maintains the burst mastership one acquired for other channels providing the request signal until the numbers of the continuous data transfers after the acquisition of the bus mastership, reaches the value set in the total-burst-number register.

A method of transferring data in a data communication system including a processor and a direct memory access controller having a plurality of channels, the method comprising the steps of:

• storing a predetermined value in a total-burst-number register in a data transfer control means of the direct memory access controller;
• setting predetermined values in burst-number registers which are part of and correspond to the plurality of channels;
• providing data transfer request signals from ones of the plurality of channels to the data transfer control means;
• generating a bus request signal from the data transfer control means to the processor in response to the reception of at least one of the data transfer request signals;
• in response to reception of the bus request signal, supplying a bus acknowledge signal from the processor to the data transfer control means, whereby the direct memory access controller acquires bus mastership;
• enabling a data transfer operation of one of the channels providing the data transfer request signals by the data transfer control means until the number of data transfer words reaches the predetermined value in the burst-number register of the one channel;
• continuously enabling a data transfer operation of the other channel providing the data transfer request signal by the data transfer control means while the data transfer control means maintains the bus membership once acquired, if the total number of the continuous data transfers, after the acquisition of the bus mastership do not reach the predetermined value of the total-burst-number register;
• and
• abandoning the bus mastership from the direct memory access controller when the total number of the continuous data transfers, after the acquisition of the bus mastership, reaches the predetermined value set in the total-burst-number register.

A method for controlling communication in a computer system which includes a host processor, a main memory and a communication control device each interconnected through a bus, the communication control device further including a control processing unit, a data memory, a circuit control unit, a data buffer, and a direct memory access controller coupled to the data memory, the data buffer and the main memory, the direct memory access controller including a first channel, a second channel and a third channel, each of the channels in turn including a status register and a burst-number register, the direct memory access controller also including a transfer control unit having a total-burst-number register, the method comprising the steps of:

• executing protocol processing of the communication control device by the central processing unit;
• storing control data for use by the central processing unit in the data memory;
• transferring serial data to and from the communication control device through the circuit control unit;
• buffering transferring of data flowing between the circuit control unit and the direct memory access controller with the data buffer, so as to absorb differences between the rate of data transfer under the control of the direct memory access controller;
• transferring the data in the data buffer to the main memory through the first channel to the direct memory access controller;
• transferring data in the main memory to the data buffer through the second channel to the direct memory access controller;
• transferring data between the data memory and the main memory through the third channel of the direct memory access controller;
• setting in the status register of each of the channels status data indicative of a data transfer enable status of each channel, wherein each of the channels provides a request signal when the status data is set into the corresponding status register;
• storing a predetermined value in the burst-number register of each of the channels, the predetermined value defining the number of data transfers in the respective channel;
• storing a predetermined value in the total-burst-number register of the transfer control unit, the predetermined value defining the number of continuous data transfers extending over at least two of the first, second, and third channels;
• issuing a burst request signal from the transfer control unit to the host processor to acquire bus mastership, upon receipt of a corresponding request signal from at least one of the first, second, and third channels;
• controlling by the transfer control unit the number of continuous data transfers in the individual channels on the basis of the predetermined value set in the corresponding burst-number register;
• and
• maintaining control of bus mastership by the transfer control unit for other channels than a first requesting channel, until the number of continuous data transfers, after the acquisition of the bus mastership, reaches the predetermined value set in the total-burst-number register.