Crosspoint matrix switching element for a packet switch

In a switching element for use in a packet switch, said element having a control circuit and a routing circuit, said routing circuit having first and second data inputs thereto and first and second data outputs therefrom, a method comprising the steps of:

• in said control circuit:
• performing, in response to first and second incoming bit streams applied on a substantially simultaneous basis to said first and second data inputs, respectively, clock signals, and a timing signal, serial bit comparisons between corresponding bits of said first and second incoming bit streams during a time window defined by said timing signal and
• generating, in response to said performing step, a control signal that assumes a pre-defined logical state upon the occurrence of a pre-determined logical condition between said first and second incoming bit streams;
• and
• in said routing circuit:
• respectively routing, in response to the first or second state of said control signal, bits comprising first and second incoming bit streams from said first and second data inputs to said first and second data outputs or to said second and first data outputs, and further
• in said control circuit:
• changing the state of said control signal from a first state to a second state, if corresponding first and second pluralities of bits being serially applied as said first and second incoming bit streams to the first and second data inputs match and subsequently thereto if a value of a third plurality of bits serially applied to the second data input exceeds a value of corresponding fourth plurality of bits serially applied to the first data input, and
• wherein said first and second pluralities of bits comprise address bits of first and second packets being serially applied to said first and second data inputs, and said third and fourth pluralities of bits comprise priority bits of said first and second packets, and
• wherein said timing signal comprises first and second timing signals, said first timing signal defining a first time window during which address bits are being serially applied from said first and second incoming bit streams to said first and second data inputs and said second timing interval defining a second time window which occurs after the first time window and during which priority bits are being serially applied from said first and second incoming bit streams to said first and second data inputs.

A packet switch comprising

• a plurality of user lines,
• a network comprising a matrix of individual switch elements, and
• means connecting said plurality of user lines to said matrix, and wherein each of said switch elements in said matrix has first and second data inputs, a timing signal input, a clock signal input, and first and second data outputs, the outputs of a switch element in said matrix being inputs to two different switch elements in said matrix, and each of switch elements further comprises
• circuit control means responsive to clock signals and to first and second incoming bit streams applied on a substantially simultaneous basis to said first and second data inputs, respectively, and a timing signal distinct from said clock signals on said timing signal input, for performing serial bit comparisons between corresponding bits of said first and second incoming bit streams during a time window defined by said timing signal and, in response thereto, for generating a control signal that assumes a state dependent upon the occurrence of a predetermined logical condition between said first and second incoming bit streams, and
• routing means responsive to said clock signals and to said control signal for routing bits comprising first and second incoming bit streams from said first and second data inputs respectively to said first and second data outputs for one state of said control signal or to said second and said first data outputs for a second state of said control signal, thereby determining to which next adjacent switch element in said matrix said data inputs are transmitted.