Large scale integrated circuit having low internal operating voltage

A semiconductor apparatus comprising:

• a well area formed in said semiconductor apparatus, the well area being of a first conductivity type, the well area being supplied with a first voltage, the first voltage being of a magnitude less than that of a second voltage supplied externally;
• a first pair of MOS transistors of a second conductivity type including a first MOS transistor and a second MOS transistor, each of the first pair having a source terminal connected to the first voltage, a drain terminal and a gate terminal, and each being formed in said well area of said semiconductor apparatus, the gate terminal of the first MOS transistor being connected to the drain terminal of the second MOS transistor and the gate terminal of the second MOS transistor being connected to the drain terminal of the first MOS transistor;
• and,
• a second pair of MOS transistors of said first conductivity type including a third MOS transistor and a fourth MOS transistor, each of the second pair having a source terminal connected to a predetermined potential, a drain terminal and a gate terminal, and each being formed in said semiconductor apparatus outside said well area, the gate terminal of the third MOS transistor being connected to the drain terminals of the fourth and second MOS transistors and the gate terminal of the fourth MOS transistor being connected to the drain terminals of the third and first MOS transistors.