US 5,179,538 AGranted

Memory system including CMOS memory cells and bipolar sensing circuit

AssigneeThe Boeing Company

InventorsRoland Pang, John Y. Chen

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Abstract

A memory system (10) is disclosed including a memory array (14), decoder circuit (16), and sensing circuit (17). The memory array includes a plurality of two-port CMOS memory cells (42) arranged in columns and rows that are selectively addressed by the decoder circuit. The bipolar sensing circuit responds to data stored in an addressed memory cell in the following manner. A column decoder (28) in the decoder circuit provides information to a source select multiplexer (30) and a column read access port (18) to selectively couple information stored in the memory cell to an output stage (20). At the output stage a comparison is made between the stored data and a reference voltage provided by a threshold circuit (38) to produce an output indicating the sensed level. The memory cells are preferably asymmetrically designed for hysteretic operation. The resultant bipolar/CMOS memory system advantageously combines the attributes of high density, high speed, and low power consumption.

Claims7

Dependent claims

A bipolar sensing circuit for use in reading information stored in an array of memory cells having read bit lines and read word lines that form a plurality of columns and rows, respectively, said information to be read from a select memory cell that is located in a select column of said array said bipolar sensing circuit comprising:

a plurality of column read transistors having base, collector, and emitter terminals, said base terminals of each of said column read transistors being coupled to a different one of said read bit lines of the memory array;
an output transistor having base, collector, and emitter terminals, said emitter terminal of said output transistor being coupled to said emitter terminal of each of said column read transistors, said column read transistors being for transferring information from a memory cell located at the intersection of one of said read bit lines and one of said read word lines to said output transistor;
current source means for drawing current from said read bit lines of said array, said current source means comprising:
(a) an output source transistor, having base, collector, and emitter terminals, said collector terminal of said output source transistor being coupled to the emitter terminals of said output transistor and said column read transistors;
(b) a select column source transistor, having base, collector, and emitter terminals, said base terminal of said select column source transistor being coupled to said base terminal of said output source transistor;
and
(c) an unselected column source transistor, having base, collector, and emitter terminals, said base terminal of said unselected column source transistor being coupled to said base terminal of said output source transistor;
and
source select means for coupling said read bit lines and said column read transistors to said current source means, said collector terminal of said select column source transistor being coupled to said source select means, said collector terminal of said unselected column source transistor being coupled to said source select means.

6 more elements

A bipolar sensing circuit for use in reading information stored in an array of memory cells having read bit lines and read word lines that form a plurality of columns and rows, respectively, and wherein information is to be read from a select memory cell that is located in a select column of said array, said bipolar sensing circuit comprising:

a plurality of column read transistors having base, collector, and emitter terminals, said base terminals of each of said column read transistors being coupled to a different one of said read bit lines of the memory array;
an output transistor having base, collector, and emitter terminals, said emitter terminal of said output transistor being coupled to said emitter terminal of each of said column read transistors, said column read transistors being for transferring information from a memory cell located at the intersection of one of said read bit lines and one of said read word lines to said output transistor;
current source means for drawing current from said read bit lines of said array, comprising a;
an output source transistor, having base, collector, and emitter terminals, said collector terminal of said output source transistor being coupled to the emitter terminals of said output transistor and said column read transistors;
a select column source transistor, having base, collector, and emitter terminals, said base terminal of said select column source transistor being coupled to said base terminal of said output source transistor;
and
an unselected column source transistor, having base, collector, and emitter terminals, said base terminal of said unselected column source transistor being coupled to said base terminal of said output source transistor;
and
source select means for coupling said read bit lines and said column read transistors to said current source means, said source select means comprising a;
a plurality of column select transistors, having base, collector, and emitter terminals, said emitter terminals of said column select transistors being coupled to said collector terminal of said select column source transistor, said collector terminals of said column select transistors respectively coupled to said base terminals of said column read transistors;
and
a plurality of column unselected transistors, having base, collector, and emitter terminals, said emitter terminals of said column unselected transistors being coupled to said collector terminal of said unselected column source transistor, said collector terminals of said column unselected transistors respectively coupled to said base terminals of said column read transistors.

9 more elements

A memory system exhibiting a high memory density and low access time, said memory system comprising:

CMOS memory means, including a plurality of memory cells arranged in an array having a plurality of columns and rows, each of said memory cells having a single data read terminal at which a bit signal stored in said memory cell can be sensed;
a plurality of read bit lines equal in number to the number of columns in said memory array, each of said read bit lines being electrically connected to said data read terminals of an associated column of said memory array;
and
single-ended bipolar sensing means, coupled to said read bit lines of said memory means, for selectively sensing information stored by said memory means, said bipolar sensing means including:
(a) column access means for coupling said bipolar sensing means to a select read bit line associated with a column of said array in which a select memory cell storing a bit signal to be sensed is located;
(b) output switching means, coupled to said column access means, for switching between states representative of the bit signal stored in said select cell;
and
(c) level establishment means, coupled to said output switching means, for applying voltage to said output switching means at levels that allow said output switching means to switch states in response to the bit signal stored in said select cell, said level establishment means comprising:
(i) threshold circuit means for applying a threshold voltage to said output switching means;
and
(ii) current source means for drawing current from said column of said array in which said select memory cell is located and for drawing current from those columns of said array in which said select memory cell is not located, said current source means comprising:
(1) a select column current source for drawing current from only said column of said array in which said select memory cell is located;
(2) an unselected column current source for drawing current from those columns of said array in which said select memory cell is not located;
and
(3) source select means for coupling said select column current source to only said column in which said select memory cell is located and for coupling said unselected column current source to those columns in which said select memory cell is not located.

12 more elements

Dependencies are inferred from the claim text.