Semiconductor memory device having monitoring function

Abstract

Memory cells providing a memory cell array are each fromed of a floating gate MOS transistor for storing data and a select MOS transistor and the memory cell is connected to a power source via a MOS transistor providing a load element. A potential on the connection node A between the load element and the memory cell is detected by an inverter providing a potential detection circuit and a monitor output is derived from the inverter. A load providing MOS transistor having a source connected to the source of the MOS transistor providing the load element and a gate connected to the gate of the MOS transistor providing the load element is provided, a pad to which a control voltage is supplied is connected to the drain of the MOS transistor and the control voltage from the pad is applied to the gates of the MOS transistors to provide a current mirror circuit.

Dependencies are inferred from the claim text.