Substrate bias voltage generating circuit including an internal frequency divider and driven by an externally applied clock signal
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorAkio Nakayama
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Abstract
A substrate bias generating circuit improved for a DRAM is disclosed. The substrate bias generating circuit is driven by an externally applied signal /RAS, and a drive pulse signal is divided by a newly provided frequency division circuit. A ratio of division of the frequency division circuit is so set that power consumed by a substrate bias generating circuit is minimized under the requirement that a potential of a substrate of the DRAM should be kept within a permissible range. Therefore, a potential of the semiconductor substrate can be kept within a permissible range under less power consumption.
Claims13
A substrate bias voltage generating circuit, comprising:
- a semiconductor substrate;
- an internal circuit formed on said substrate;
- an internal clock signal generating means responsive to an externally applied clock signal for generating an internal clock signal for controlling said internal circuit;
- frequency divider means connected to receive said internal clock signal for dividing said internal clock signal by a predetermined ratio of division;
- substrate bias voltage generating means connected to an output of said frequency divider means and driven by the divided internal clock signal for generating a substrate bias voltage to keep a potential of said substrate in a predetermined range.
A semiconductor integrated circuit device, comprising:
- a semiconductor substrate;
- function circuit means formed on said substrate for implementing predetermined circuit functions;
- internal clock signal generating means responsive to an externally applied clock signal for generating an internal clock signal for controlling said function circuit means;
- frequency divider means connected to receive said internal clock signal for dividing said internal clock signal by a predetermined ratio of division;
- and
- a substrate bias voltage generating means connected to an output of said frequency divider means and driven by the divided internal clock signal for generating a substrate bias voltage to keep a potential of said substrate within a predetermined range.
Dependencies are inferred from the claim text.