Integrated PNP power bipolar transistor with low injection into substrate
AssigneeMicrel, Inc.
InventorJohn Husher
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AssigneeMicrel, Inc.
InventorJohn Husher
Estimating the term…
In one embodiment of the invention, a P buried region is formed in an N epitaxial layer and isolated from a P substrate by an N buried region. P+ emitters and P+ collectors are formed in the surface of the N epitaxial layer (acting as a base). The P buried region acts as a catch diffusion for minority hole carriers injected into the epitaxial layer by the surface emitters that escape collection by the surface P+ collectors and which would otherwise be injected into the substrate. The N buried region effectively isolates the P buried region from the P substrate and further blocks any minority carriers from being injected into the substrate. The P buried region also prevents the formation of a parasitic PNP transistor to the substrate of the integrated device. This further reduces substrate current and thus further reduces the possibility of noise and latchup. The resulting structure is an efficient high power integrated PNP bipolar transistor capable of being incorporated in integrated circuits with very sensitive low power logic devices.
A high voltage bipolar transistor structure comprising:
Dependencies are inferred from the claim text.