Circuit arrangement for the compensation of the control current of a transistor

Abstract

A circuit for the compensation of a control current of a first transistor whose main current path is arranged in series with a main current path of a second transistor between two supply voltage terminals. The arrangement includes a current mirror circuit including two transistors having a common terminal connected to the one supply voltage terminal which is coupled to the second transistor. The input terminal of the current mirror is connected to a control terminal of the second transistor and its output terminal is arranged to supply a compensation current to a control terminal of the first transistor. The circuit provides an optimum compensation for the control current of the transistor amplifier (first transistor) and even in the case of low supply voltages produces a maximal signal output swing of the first transistor by the provision of a third transistor via whose main current path the compensation current is supplied and whose control terminal is connected to a node between the main current paths of the first transistor and the second transistor.

Dependencies are inferred from the claim text.