Method and apparatus for analog testing

A method of testing a TFT/LCD including a cell comprised of a cell capacitor, and a thin film transistor including a gate, a source and a drain, wherein said drain is connected to said cell capacitor, using a sense circuit comprising an integrator means and reset means wherein said integrator means is selectively coupled to said drain through a data line, said method comprising the steps of:

• turning off said thin film transistor by applying a first predetermined gate voltage to said gate;
• resetting said integrator using said reset circuit;
• raising the voltage on said drain to a value sufficient to charge said cell capacitor;
• applying a second predetermined gate voltage to said gate sufficient to turn on said transistor;
• waiting a first predetermined time period sufficient to charge said cell capacitor to a predetermined test value;
• applying said first gate voltage to said gate to turn said transistor off;
• waiting a second predetermined period of time;
• lowering said voltage on said drain to approximately ground potential during said second period of time;
• disconnecting said voltage on said drain during said second period of time;
• applying said second gate voltage to said gate to turn said transistor on;
• waiting a third predetermined period of time;
• applying said first gate voltage to said gate to turn said transistor off;
• measuring a potential at an output of said integrator means.

A method of testing thin film transistors using a test circuit, said thin film transistor comprising:

• a gate connected to a gate terminal through a gate line;
• a drain connected to a drain terminal through a data line;
• a source connected to a cell capacitance through a source terminal;
• said test circuit, including an input terminal and an output terminal and comprising:
• an operational amplifier including non-inverting and inverting input terminals and an output terminal, said output terminal being connected to said test circuit output terminal and said non-inverting terminal being connected to a ground potential;
• an integrating capacitor connected between said inverting input terminal and said output terminal;
• a first controllable switch connected between a first potential and said test circuit input terminal;
• a second controllable switch connected between said inverting input terminal and said test circuit input terminal;
• a third controllable switch connected between said inverting input terminal and said test circuit output terminal;
• said method comprising the steps of:
• opening said second switch;
• closing said third switch;
• closing said first switch;
• waiting a first predetermined time period, wherein said first time period corresponds to a time constant of said data line;
• applying a voltage to said gate terminal sufficient to bias said transistor on;
• waiting a second predetermined time period, wherein said second time period corresponds to the test time period for said thin film transistor;
• applying a voltage to said gate terminal sufficient to bias said transistor off;
• closing said second switch for a third predetermined time period, corresponding to a test hold time;
• open said third switch after a fourth predetermined time period;
• applying a voltage to said gate sufficient to turn said transistor on;
• waiting a fifth predetermined time sufficient to transfer charge from said cell capacitance to said integrating capacitor;
• applying a voltage to said gate sufficient to turn said transistor off;
• waiting a sixth predetermined time, corresponding to the RC time constant of said gate line;
• sampling said output node.

A circuit for electrically activating and measuring characteristics of a cell of a liquid crystal display, wherein said cell has associated therewith a cell capacitor and a thin film transistor, said thin film transistor having a source, a gate and a drain, said circuit comprising:

• means for supplying energy for driving the gate of said thin film transistor,
• means for supplying charge through said source and drain of said thin film transistor to said cell capacitor at a predetermined time;
• an integrating circuit coupled to said cell capacitor for integrating voltage thereon;
• and
• a reset circuit for resetting said integrating circuit prior to integrating.

A method for electrically testing a liquid crystal display cell having a cell capacitor and a thin film transistor associated therewith, wherein said thin film transistor has a source, a gate and a drain, said method comprising the steps of:

• supplying energy for driving the gate of said thin film transistor;
• depositing charge through said source and drain of said thin film transistor on said cell capacitor at a predetermined time;
• integrating a voltage level on said cell capacitor over a period of time by using an integrator coupled to said cell capacitor;
• and
• resetting the integrator before integrating.

A method for electrically testing a liquid crystal display cell having a cell capacitor and a thin film transistor associated therewith, wherein said thin film transistor has a source, a gate and a drain, the method comprising:

• electrically connecting said liquid crystal display cell to said integrator with a test fixture;
• supplying energy for driving the gate of said thin film transistor;
• depositing charge through said source and drain of said thin film transistor on said cell capacitor at a predetermined time;
• integrating a voltage level on said cell capacitor over a period of time by using an integrator coupled to said cell capacitor to produce a first integrated voltage;
• resetting the integrator before integrating off;
• depositing charge on a portion of said test fixture used to electrically connect said integrator to said cell and on a data line of said cell;
• resetting said integrator;
• integrating a voltage level on said portion of said test fixture and said data line over a period of time to produce a second integrated voltage;
• and
• subtracting said second integrated voltage from said first integrated voltage.