CMOS low output voltage bus driver
AssigneeNCR Corporation
InventorDonald G. Tipon
Life of this patent
Estimating the term…
Abstract
In a high speed digital computer data transfer system, a data bus driver reduces data bus voltage swings between logic high and logic low levels by defining minimum and maximum bus voltages which lie between said logic levels, thus lowering bus transition and hence data transfer times. Positive and negative overshoot of the reduced bus logic levels are prevented by "clamping diode" transistors. The data bus driver assumes a tri-state mode when not transmitting data, during which the clamping diode transistors also eliminate positive and negative bus voltage overshoot. The preferred embodiment is implemented using complementary metal-oxide-semiconductor (CMOS) technology.
Claims8
A high speed digital computer data transfer system for transferring data, said data transfer system having reduced bus state transition time and comprising:
- a driver which receives said data in the form of first and second logic level signals and converts said data to third and fourth logic levels wherein said third and fourth logic levels define a range which is less than a range defined by said first and second logic levels;
- an output node coupled to said driver for transferring said third and fourth logic level signals;
- and
- a clamping means coupled to said output node for preventing a voltage on said output node from transcending a range defined by said third and fourth logic levels.
Dependencies are inferred from the claim text.