Method of forming integrated leadouts for a chip carrier

Abstract

A method of forming leadouts on a surface mountable chip carrier for electrical connection to a supporting substrate, such as a motherboard. The chip carrier includes a carrier board having input/output vias extending to a selected layer of the carrier board. In a preferred embodiment, the selected layer is the lower surface of the carrier board, but the selected layer may optionally be the upper surface or an intermediate layer. The input/output vias are on an inboard side of an interconnection region. An array of terminals, which may also be vias, are on the outboard side of the interconnection region. The interconnection region is removed from the carrier board to form a window located between the terminals and the input/output vias. In the preferred embodiment, a metallic layer is then deposited on the lower surface of the carrier board. The metallic layer is patterned to leave leads extending from the input/output vias to the terminals, thereby providing parallel leads extending across the window. The portion of the leads exposed by the window provides contact sites to be bonded to contact sites of the supporting substrate. Preferably, a number of windows are formed. The portion of the carrier board that is outboard of the windows may optionally be removed to form cantilevered input/output leads of a leaded chip carrier.

Dependencies are inferred from the claim text.