High resolution symmetrical divider circuit

A divider circuit for dividing a recurrent digital clocking signal into a quotient digital signal having a substantially symmetrical duty cycle within a range of programmable quotients, the quotients being selectable in single increments of the recurrent digital clocking signal within a range as selected by a divisor, comprising:

• register means for holding the divisor,
• down counting means for receiving the divisor from the register means for down counting from the divisor to zero in synchronism with the recurrent digital clocking signal,
• bistable latch means set to a first state by a first state logical signal occurring coincidently with a beginning of the down counting means to count down from the divisor, the latch means for putting out the quotient digital signal,
• divide-by-two divider means for dividing the divisor by two to provide a half-count value,
• comparator means for comparing the half-count value with a count reached by the down counting means and for generating a second state logical signal upon detected equivalence of the half-count value and the count reached,
• the bistable latch means being set by the second state logical signal to a second state opposite said first state, until the first state logical signal occurs, whereupon operation of the circuit repeats.