Personal computer memory bank parity error indicator
AssigneeInternational Business Machines Corporation
InventorsLouis B. Capps, Jr., Jimmy G. Foster, Warren E. Price, Robert W. Rupe, Kenneth A. Uplinger
Life of this patent
Estimating the term…
Abstract
A personal computer has two memory banks respectively connected to two parity check units operative to detect parity errors. Upon doing so, each unit feeds a parity error signal to a separate latch. The latches are connected to a logic circuit which is in turn connected to an interrupt controller that initiates an interrupt when a parity error occurs. One latch is further connected to a check bit of a register of an I/O port and the check bit is set by the one latch. An interrupt handler reads the register and provides messages indicating which memory bank caused the parity error.
Claims5
In a personal computer having an interruptable microprocessor, and a main memory comprising first and second memory banks which are simultaneously accessed during each memory access, a memory bank parity error indicating system for indicating which memory bank caused a parity error during a memory access, comprising:
- first and second parity check units respectively connected to said first and second memory banks, said first parity check unit being operative to generate a first parity error signal upon detecting a parity error in data being accessed in said first memory bank, said second parity check unit being operative to generate a second parity error signal upon detecting a parity error in data being accessed in said second memory bank;
- first means connected to said first and second parity check units and to said microprocessor, said first means being operative in response to either of said parity check units generating a parity error signal to transmit a parity error interrupt signal to said microprocessor;
- a single bit storage device for storing a check bit for indicating which one of said first and second memory banks was being accessed during a single memory access in which a parity error occurs, said check bit being switchable between a first state and a second state;
- second means connected between said first parity check unit and said storage device for switching said check bit from said second state to said first state only in response to said first parity check unit generating said first parity error signal;
- and parity error interrupt handling means connected to said storage device and being operative in response to said microprocessor receiving said parity error interrupt signal to read said check bit and determine from said state of said check bit which one of said first and second memory banks caused the parity error during said memory access, said parity error interrupt handling means determining said first memory bank caused the parity error when said check bit is in said first state and determining said second memory bank caused the parity error when said check bit is in said second state.
Dependencies are inferred from the claim text.