Memory device with a test mode

A memory device, comprising:

• (A) a memory array;
• (B) an address buffer for storing a plurality of bits of an address for addressing the memory array, wherein the address is applied as an input of the address buffer, wherein each bit of the address can be in a first voltage state, a second voltage state, and a third voltage state;
• (C) a first circuit for detecting the state of any bit of the address and for triggering the test mode if the third voltage state is detected on at least one of the plurality of bits of the address;
• and
• (D) a second circuit for allowing the entire memory array to be addressed, wherein the second circuit detects the state of one bit of the address and converts one corresponding address bit stored in the address buffer to the second voltage state if the one bit of the address is in the third voltage state, wherein the second circuit detects the state of two bits of the address and converts two corresponding address bits stored in the address buffer to the first voltage state if the two bits of the address are in the third voltage state, wherein the second circuit is coupled to the address buffer.

A method of triggering a test mode of a memory device comprising the steps of:

• (A) addressing a memory array of the memory device by applying an address of a plurality of bits to an address buffer, wherein the address is applied as an input of the address buffer, wherein each bit of the address can be in a first voltage state, a second voltage state, and a third voltage state;
• (B) detecting the state of any bit of the address and triggering the test mode if the third voltage state is detected on at least one of the plurality of bits of the address;
• and
• (C) allowing the entire memory array to be addressed by detecting the state of two bits of the address and converting two corresponding address bits stored in the address buffer to the first voltage state if the two bits of the address are in the third voltage state, and by detecting the state of one bit of the address and converting one corresponding address bit stored in the address buffer to the second voltage state if the one bit of the address is in the third voltage state.