Method and apparatus for error recovery in arrays
AssigneeInternational Business Machines Corporation
InventorsBrian K. Cesare, Timothy J. Slegel, Darell S. Whitaker
Life of this patent
Estimating the term…
Abstract
Method and apparatus for error recovery in primary storage is provided by backup storage that stores a complete copy of primary storage. When a parity error is detected, the backup storage is used to replace data in the primary storage or the parity of primary storage. This apparatus is controlled by a processor controller which makes this replacement by comparing the primary storage, backup storage, and the primary parity storage. If after re-execution of the operation errors are still detected, the processor controller copies the data from primary storage to a second storage and retries the operation.
Claims14
A method for error recovery in primary vector data array register wherein said register includes a plurality of interleaved primary array chips comprising the steps of:
- providing a backup array chip,
- writing data into said primary array chips and at the same time writing identical data into the corresponding location in said backup array chip,
- providing and storing in a plurality of interleaved parity array chips parity for each element stored in said primary array chips,
- as data is read out of said primary array chips, parity checking is done with the data stored in the parity array chips,
- if a parity array error is detected by the logic stopping all processing, comparing and processing the elements from the primary data array chips, the corresponding data element from the backup array chips, and the corresponding parity from the parity array chips as follows:
- if the data in the backup array chips agrees with that in the parity array chips, correcting the element in the primary array chips to correspond with the corresponding element the backup array chips,
- if the backup array data element equals that in the primary array chips, correcting the parity in the parity element,
- if the failure was one of the last two steps, retrying the instruction, and
- if the instruction is not successful after a predetermined plurality of attempts, placing a copy of the data from the backup array chips in a second address space of the primary array chips and generating new parity for the parity array chips based on said copy.
A method for error recovery in a storage system, said system having a primary data array containing primary data, a parity data array containing parity data associated with said primary data, and a backup data array containing a complete copy of said primary data, said method comprising:
- reading requested data from said primary data array and its associated parity data from said parity data array;
- checking for a parity error upon said reading of said requested data;
- stopping processing if a parity error is detected and performing the following steps;
- re-reading said requested data from said primary and parity arrays;
- reading a copy of said requested data from said backup data array;
- and
- continuing processing if no parity error is detected after said re-read of said requested data.
A method for error recovery in a storage system, said system having a primary data array containing primary data, a parity data array containing parity data associated with said primary data, and a backup data array containing a complete copy of said primary data, each of said primary data array and said parity data array being divided into a primary address space and a secondary address space, said method comprising:
- reading requested data from said primary address space of said primary data array and reading its associated parity data from said primary address space of said parity data array;
- checking for a parity error upon said reading of said requested data;
- stopping processing if a parity error is detected and performing the following steps;
- re-reading said requested data from said primary address spaces of said primary data array and parity data array;
- reading a copy of said requested data from said backup data array;
- and
- continuing processing if no parity error is detected after said re-read of said requested data.
A storage system comprising:
- a primary data storage for storing data elements;
- a parity storage for storing parity for each of said data elements stored in said primary data storage;
- a backup storage for storing a complete copy of what is stored in said primary data storage;
- input and output registers connected to each of said storages;
- a processor controller;
- and
- said input and output registers connected in series with said processor controller.
In a vector processing system including a processor and a processor controller, a vector register system comprising;
- a primary data array formed on a first plurality of array chips, said primary data array having a primary address space and a secondary address space;
- said primary data array containing data elements stored in an interleaved distributed fashion over said plurality of array chips;
- a parity data array formed on a second plurality of array chips, said parity data array storing parity data for each of said data elements stored in said primary data array;
- a backup data array containing a complete copy of said data elements in said primary data space in said primary array;
- a first means for comparing parity of a particular data element in said primary data array and its associated parity in said parity data array;
- a second means for comparing parity of a copy of said particular data element in said backup data array and its associated parity in said parity data array;
- a third means for replacing said particular data element in said primary data array with said copy of said particular data element from said backup array if a parity error is detected in said first means and no parity error is detected in said second means;
- and
- a fourth means for replacing said associated parity if no parity error is detected in said first or second means.
Dependencies are inferred from the claim text.